spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-exynos / setup-fimc.c
blob6a45078d9d128968f579cfe374b76374d1840fca
1 /*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
4 * Exynos4 camera interface GPIO configuration.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #include <linux/gpio.h>
12 #include <plat/gpio-cfg.h>
13 #include <plat/camport.h>
15 int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
17 u32 gpio8, gpio5;
18 u32 sfn;
19 int ret;
21 switch (id) {
22 case S5P_CAMPORT_A:
23 gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
24 gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
25 sfn = S3C_GPIO_SFN(2);
26 break;
28 case S5P_CAMPORT_B:
29 gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
30 gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
31 sfn = S3C_GPIO_SFN(3);
32 break;
34 default:
35 WARN(1, "Wrong camport id: %d\n", id);
36 return -EINVAL;
39 ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
40 if (ret)
41 return ret;
43 return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);