spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-exynos / setup-fimd0.c
blob07a6dbeecdd081998be213f2b5ecacf90b3d7a78
1 /* linux/arch/arm/mach-exynos4/setup-fimd0.c
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Base Exynos4 FIMD 0 configuration
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/fb.h>
14 #include <linux/gpio.h>
16 #include <plat/gpio-cfg.h>
17 #include <plat/regs-fb-v4.h>
19 #include <mach/map.h>
21 void exynos4_fimd0_gpio_setup_24bpp(void)
23 unsigned int reg;
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
26 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
28 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
31 * Set DISPLAY_CONTROL register for Display path selection.
33 * DISPLAY_CONTROL[1:0]
34 * ---------------------
35 * 00 | MIE
36 * 01 | MDINE
37 * 10 | FIMD : selected
38 * 11 | FIMD
40 reg = __raw_readl(S3C_VA_SYS + 0x0210);
41 reg |= (1 << 1);
42 __raw_writel(reg, S3C_VA_SYS + 0x0210);