arch/arm/mach-footbridge/common.c

   1 /*
   2  *  linux/arch/arm/mach-footbridge/common.c
   3  *
   4  *  Copyright (C) 1998-2000 Russell King, Dave Gilbert.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/mm.h>
  13 #include <linux/ioport.h>
  14 #include <linux/list.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <asm/pgtable.h>
  20 #include <asm/page.h>
  21 #include <asm/irq.h>
  22 #include <asm/mach-types.h>
  23 #include <asm/setup.h>
  24 #include <asm/hardware/dec21285.h>
  25
  26 #include <asm/mach/irq.h>
  27 #include <asm/mach/map.h>
  28
  29 #include "common.h"
  30
  31 unsigned int mem_fclk_21285 = 50000000;
  32
  33 EXPORT_SYMBOL(mem_fclk_21285);
  34
  35 static int __init early_fclk(char *arg)
  36 {
  37         mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
  38         return 0;
  39 }
  40
  41 early_param("mem_fclk_21285", early_fclk);
  42
  43 static int __init parse_tag_memclk(const struct tag *tag)
  44 {
  45         mem_fclk_21285 = tag->u.memclk.fmemclk;
  46         return 0;
  47 }
  48
  49 __tagtable(ATAG_MEMCLK, parse_tag_memclk);
  50
  51 /*
  52  * Footbridge IRQ translation table
  53  *  Converts from our IRQ numbers into FootBridge masks
  54  */
  55 static const int fb_irq_mask[] = {
  56         IRQ_MASK_UART_RX,       /*  0 */
  57         IRQ_MASK_UART_TX,       /*  1 */
  58         IRQ_MASK_TIMER1,        /*  2 */
  59         IRQ_MASK_TIMER2,        /*  3 */
  60         IRQ_MASK_TIMER3,        /*  4 */
  61         IRQ_MASK_IN0,           /*  5 */
  62         IRQ_MASK_IN1,           /*  6 */
  63         IRQ_MASK_IN2,           /*  7 */
  64         IRQ_MASK_IN3,           /*  8 */
  65         IRQ_MASK_DOORBELLHOST,  /*  9 */
  66         IRQ_MASK_DMA1,          /* 10 */
  67         IRQ_MASK_DMA2,          /* 11 */
  68         IRQ_MASK_PCI,           /* 12 */
  69         IRQ_MASK_SDRAMPARITY,   /* 13 */
  70         IRQ_MASK_I2OINPOST,     /* 14 */
  71         IRQ_MASK_PCI_ABORT,     /* 15 */
  72         IRQ_MASK_PCI_SERR,      /* 16 */
  73         IRQ_MASK_DISCARD_TIMER, /* 17 */
  74         IRQ_MASK_PCI_DPERR,     /* 18 */
  75         IRQ_MASK_PCI_PERR,      /* 19 */
  76 };
  77
  78 static void fb_mask_irq(struct irq_data *d)
  79 {
  80         *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
  81 }
  82
  83 static void fb_unmask_irq(struct irq_data *d)
  84 {
  85         *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
  86 }
  87
  88 static struct irq_chip fb_chip = {
  89         .irq_ack        = fb_mask_irq,
  90         .irq_mask       = fb_mask_irq,
  91         .irq_unmask     = fb_unmask_irq,
  92 };
  93
  94 static void __init __fb_init_irq(void)
  95 {
  96         unsigned int irq;
  97
  98         /*
  99          * setup DC21285 IRQs
 100          */
 101         *CSR_IRQ_DISABLE = -1;
 102         *CSR_FIQ_DISABLE = -1;
 103
 104         for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
 105                 irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
 106                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 107         }
 108 }
 109
 110 void __init footbridge_init_irq(void)
 111 {
 112         __fb_init_irq();
 113
 114         if (!footbridge_cfn_mode())
 115                 return;
 116
 117         if (machine_is_ebsa285())
 118                 /* The following is dependent on which slot
 119                  * you plug the Southbridge card into.  We
 120                  * currently assume that you plug it into
 121                  * the right-hand most slot.
 122                  */
 123                 isa_init_irq(IRQ_PCI);
 124
 125         if (machine_is_cats())
 126                 isa_init_irq(IRQ_IN2);
 127
 128         if (machine_is_netwinder())
 129                 isa_init_irq(IRQ_IN3);
 130 }
 131
 132 /*
 133  * Common mapping for all systems.  Note that the outbound write flush is
 134  * commented out since there is a "No Fix" problem with it.  Not mapping
 135  * it means that we have extra bullet protection on our feet.
 136  */
 137 static struct map_desc fb_common_io_desc[] __initdata = {
 138         {
 139                 .virtual        = ARMCSR_BASE,
 140                 .pfn            = __phys_to_pfn(DC21285_ARMCSR_BASE),
 141                 .length         = ARMCSR_SIZE,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = XBUS_BASE,
 145                 .pfn            = __phys_to_pfn(0x40000000),
 146                 .length         = XBUS_SIZE,
 147                 .type           = MT_DEVICE,
 148         }
 149 };
 150
 151 /*
 152  * The mapping when the footbridge is in host mode.  We don't map any of
 153  * this when we are in add-in mode.
 154  */
 155 static struct map_desc ebsa285_host_io_desc[] __initdata = {
 156 #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
 157         {
 158                 .virtual        = PCIMEM_BASE,
 159                 .pfn            = __phys_to_pfn(DC21285_PCI_MEM),
 160                 .length         = PCIMEM_SIZE,
 161                 .type           = MT_DEVICE,
 162         }, {
 163                 .virtual        = PCICFG0_BASE,
 164                 .pfn            = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
 165                 .length         = PCICFG0_SIZE,
 166                 .type           = MT_DEVICE,
 167         }, {
 168                 .virtual        = PCICFG1_BASE,
 169                 .pfn            = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
 170                 .length         = PCICFG1_SIZE,
 171                 .type           = MT_DEVICE,
 172         }, {
 173                 .virtual        = PCIIACK_BASE,
 174                 .pfn            = __phys_to_pfn(DC21285_PCI_IACK),
 175                 .length         = PCIIACK_SIZE,
 176                 .type           = MT_DEVICE,
 177         }, {
 178                 .virtual        = PCIO_BASE,
 179                 .pfn            = __phys_to_pfn(DC21285_PCI_IO),
 180                 .length         = PCIO_SIZE,
 181                 .type           = MT_DEVICE,
 182         },
 183 #endif
 184 };
 185
 186 void __init footbridge_map_io(void)
 187 {
 188         /*
 189          * Set up the common mapping first; we need this to
 190          * determine whether we're in host mode or not.
 191          */
 192         iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
 193
 194         /*
 195          * Now, work out what we've got to map in addition on this
 196          * platform.
 197          */
 198         if (footbridge_cfn_mode())
 199                 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
 200 }
 201
 202 void footbridge_restart(char mode, const char *cmd)
 203 {
 204         if (mode == 's') {
 205                 /* Jump into the ROM */
 206                 soft_restart(0x41000000);
 207         } else {
 208                 /*
 209                  * Force the watchdog to do a CPU reset.
 210                  *
 211                  * After making sure that the watchdog is disabled
 212                  * (so we can change the timer registers) we first
 213                  * enable the timer to autoreload itself.  Next, the
 214                  * timer interval is set really short and any
 215                  * current interrupt request is cleared (so we can
 216                  * see an edge transition).  Finally, TIMER4 is
 217                  * enabled as the watchdog.
 218                  */
 219                 *CSR_SA110_CNTL &= ~(1 << 13);
 220                 *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
 221                                    TIMER_CNTL_AUTORELOAD |
 222                                    TIMER_CNTL_DIV16;
 223                 *CSR_TIMER4_LOAD = 0x2;
 224                 *CSR_TIMER4_CLR  = 0;
 225                 *CSR_SA110_CNTL |= (1 << 13);
 226         }
 227 }
 228
 229 #ifdef CONFIG_FOOTBRIDGE_ADDIN
 230
 231 static inline unsigned long fb_bus_sdram_offset(void)
 232 {
 233         return *CSR_PCISDRAMBASE & 0xfffffff0;
 234 }
 235
 236 /*
 237  * These two functions convert virtual addresses to PCI addresses and PCI
 238  * addresses to virtual addresses.  Note that it is only legal to use these
 239  * on memory obtained via get_zeroed_page or kmalloc.
 240  */
 241 unsigned long __virt_to_bus(unsigned long res)
 242 {
 243         WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
 244
 245         return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
 246 }
 247 EXPORT_SYMBOL(__virt_to_bus);
 248
 249 unsigned long __bus_to_virt(unsigned long res)
 250 {
 251         res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
 252
 253         WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
 254
 255         return res;
 256 }
 257 EXPORT_SYMBOL(__bus_to_virt);
 258
 259 unsigned long __pfn_to_bus(unsigned long pfn)
 260 {
 261         return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
 262 }
 263 EXPORT_SYMBOL(__pfn_to_bus);
 264
 265 unsigned long __bus_to_pfn(unsigned long bus)
 266 {
 267         return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
 268 }
 269 EXPORT_SYMBOL(__bus_to_pfn);
 270
 271 #endif