spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-iop32x / irq.c
blobd7ee2789d890a19b1db52f3015db818188de4c78
1 /*
2 * arch/arm/mach-iop32x/irq.c
4 * Generic IOP32X IRQ handling functionality
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <asm/mach/irq.h>
18 #include <asm/irq.h>
19 #include <mach/hardware.h>
20 #include <asm/mach-types.h>
22 static u32 iop32x_mask;
24 static void intctl_write(u32 val)
26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
29 static void intstr_write(u32 val)
31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
34 static void
35 iop32x_irq_mask(struct irq_data *d)
37 iop32x_mask &= ~(1 << d->irq);
38 intctl_write(iop32x_mask);
41 static void
42 iop32x_irq_unmask(struct irq_data *d)
44 iop32x_mask |= 1 << d->irq;
45 intctl_write(iop32x_mask);
48 struct irq_chip ext_chip = {
49 .name = "IOP32x",
50 .irq_ack = iop32x_irq_mask,
51 .irq_mask = iop32x_irq_mask,
52 .irq_unmask = iop32x_irq_unmask,
55 void __init iop32x_init_irq(void)
57 int i;
59 iop_init_cp6_handler();
61 intctl_write(0);
62 intstr_write(0);
63 if (machine_is_glantank() ||
64 machine_is_iq80321() ||
65 machine_is_iq31244() ||
66 machine_is_n2100() ||
67 machine_is_em7210())
68 *IOP3XX_PCIIRSR = 0x0f;
70 for (i = 0; i < NR_IRQS; i++) {
71 irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
72 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);