arch/arm/mach-ixp4xx/common-pci.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common-pci.c
   3  *
   4  * IXP4XX PCI routines for all platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright (C) 2002 Intel Corporation.
   9  * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
  10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  */
  17
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mm.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/device.h>
  28 #include <linux/io.h>
  29 #include <linux/export.h>
  30 #include <asm/dma-mapping.h>
  31
  32 #include <asm/cputype.h>
  33 #include <asm/irq.h>
  34 #include <asm/sizes.h>
  35 #include <asm/system.h>
  36 #include <asm/mach/pci.h>
  37 #include <mach/hardware.h>
  38
  39
  40 /*
  41  * IXP4xx PCI read function is dependent on whether we are
  42  * running A0 or B0 (AppleGate) silicon.
  43  */
  44 int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  45
  46 /*
  47  * Base address for PCI regsiter region
  48  */
  49 unsigned long ixp4xx_pci_reg_base = 0;
  50
  51 /*
  52  * PCI cfg an I/O routines are done by programming a
  53  * command/byte enable register, and then read/writing
  54  * the data from a data regsiter. We need to ensure
  55  * these transactions are atomic or we will end up
  56  * with corrupt data on the bus or in a driver.
  57  */
  58 static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
  59
  60 /*
  61  * Read from PCI config space
  62  */
  63 static void crp_read(u32 ad_cbe, u32 *data)
  64 {
  65         unsigned long flags;
  66         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  67         *PCI_CRP_AD_CBE = ad_cbe;
  68         *data = *PCI_CRP_RDATA;
  69         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  70 }
  71
  72 /*
  73  * Write to PCI config space
  74  */
  75 static void crp_write(u32 ad_cbe, u32 data)
  76 {
  77         unsigned long flags;
  78         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  79         *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
  80         *PCI_CRP_WDATA = data;
  81         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  82 }
  83
  84 static inline int check_master_abort(void)
  85 {
  86         /* check Master Abort bit after access */
  87         unsigned long isr = *PCI_ISR;
  88
  89         if (isr & PCI_ISR_PFE) {
  90                 /* make sure the Master Abort bit is reset */
  91                 *PCI_ISR = PCI_ISR_PFE;
  92                 pr_debug("%s failed\n", __func__);
  93                 return 1;
  94         }
  95
  96         return 0;
  97 }
  98
  99 int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
 100 {
 101         unsigned long flags;
 102         int retval = 0;
 103         int i;
 104
 105         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 106
 107         *PCI_NP_AD = addr;
 108
 109         /*
 110          * PCI workaround  - only works if NP PCI space reads have
 111          * no side effects!!! Read 8 times. last one will be good.
 112          */
 113         for (i = 0; i < 8; i++) {
 114                 *PCI_NP_CBE = cmd;
 115                 *data = *PCI_NP_RDATA;
 116                 *data = *PCI_NP_RDATA;
 117         }
 118
 119         if(check_master_abort())
 120                 retval = 1;
 121
 122         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 123         return retval;
 124 }
 125
 126 int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
 127 {
 128         unsigned long flags;
 129         int retval = 0;
 130
 131         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 132
 133         *PCI_NP_AD = addr;
 134
 135         /* set up and execute the read */
 136         *PCI_NP_CBE = cmd;
 137
 138         /* the result of the read is now in NP_RDATA */
 139         *data = *PCI_NP_RDATA;
 140
 141         if(check_master_abort())
 142                 retval = 1;
 143
 144         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 145         return retval;
 146 }
 147
 148 int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
 149 {
 150         unsigned long flags;
 151         int retval = 0;
 152
 153         raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
 154
 155         *PCI_NP_AD = addr;
 156
 157         /* set up the write */
 158         *PCI_NP_CBE = cmd;
 159
 160         /* execute the write by writing to NP_WDATA */
 161         *PCI_NP_WDATA = data;
 162
 163         if(check_master_abort())
 164                 retval = 1;
 165
 166         raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
 167         return retval;
 168 }
 169
 170 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
 171 {
 172         u32 addr;
 173         if (!bus_num) {
 174                 /* type 0 */
 175                 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
 176                     (where & ~3);
 177         } else {
 178                 /* type 1 */
 179                 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
 180                         ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
 181         }
 182         return addr;
 183 }
 184
 185 /*
 186  * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
 187  * 0 and 3 are not valid indexes...
 188  */
 189 static u32 bytemask[] = {
 190         /*0*/   0,
 191         /*1*/   0xff,
 192         /*2*/   0xffff,
 193         /*3*/   0,
 194         /*4*/   0xffffffff,
 195 };
 196
 197 static u32 local_byte_lane_enable_bits(u32 n, int size)
 198 {
 199         if (size == 1)
 200                 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
 201         if (size == 2)
 202                 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
 203         if (size == 4)
 204                 return 0;
 205         return 0xffffffff;
 206 }
 207
 208 static int local_read_config(int where, int size, u32 *value)
 209 {
 210         u32 n, data;
 211         pr_debug("local_read_config from %d size %d\n", where, size);
 212         n = where % 4;
 213         crp_read(where & ~3, &data);
 214         *value = (data >> (8*n)) & bytemask[size];
 215         pr_debug("local_read_config read %#x\n", *value);
 216         return PCIBIOS_SUCCESSFUL;
 217 }
 218
 219 static int local_write_config(int where, int size, u32 value)
 220 {
 221         u32 n, byte_enables, data;
 222         pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
 223         n = where % 4;
 224         byte_enables = local_byte_lane_enable_bits(n, size);
 225         if (byte_enables == 0xffffffff)
 226                 return PCIBIOS_BAD_REGISTER_NUMBER;
 227         data = value << (8*n);
 228         crp_write((where & ~3) | byte_enables, data);
 229         return PCIBIOS_SUCCESSFUL;
 230 }
 231
 232 static u32 byte_lane_enable_bits(u32 n, int size)
 233 {
 234         if (size == 1)
 235                 return (0xf & ~BIT(n)) << 4;
 236         if (size == 2)
 237                 return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
 238         if (size == 4)
 239                 return 0;
 240         return 0xffffffff;
 241 }
 242
 243 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 244 {
 245         u32 n, byte_enables, addr, data;
 246         u8 bus_num = bus->number;
 247
 248         pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
 249                 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
 250
 251         *value = 0xffffffff;
 252         n = where % 4;
 253         byte_enables = byte_lane_enable_bits(n, size);
 254         if (byte_enables == 0xffffffff)
 255                 return PCIBIOS_BAD_REGISTER_NUMBER;
 256
 257         addr = ixp4xx_config_addr(bus_num, devfn, where);
 258         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
 259                 return PCIBIOS_DEVICE_NOT_FOUND;
 260
 261         *value = (data >> (8*n)) & bytemask[size];
 262         pr_debug("read_config_byte read %#x\n", *value);
 263         return PCIBIOS_SUCCESSFUL;
 264 }
 265
 266 static int ixp4xx_pci_write_config(struct pci_bus *bus,  unsigned int devfn, int where, int size, u32 value)
 267 {
 268         u32 n, byte_enables, addr, data;
 269         u8 bus_num = bus->number;
 270
 271         pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
 272                 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
 273
 274         n = where % 4;
 275         byte_enables = byte_lane_enable_bits(n, size);
 276         if (byte_enables == 0xffffffff)
 277                 return PCIBIOS_BAD_REGISTER_NUMBER;
 278
 279         addr = ixp4xx_config_addr(bus_num, devfn, where);
 280         data = value << (8*n);
 281         if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
 282                 return PCIBIOS_DEVICE_NOT_FOUND;
 283
 284         return PCIBIOS_SUCCESSFUL;
 285 }
 286
 287 struct pci_ops ixp4xx_ops = {
 288         .read =  ixp4xx_pci_read_config,
 289         .write = ixp4xx_pci_write_config,
 290 };
 291
 292 /*
 293  * PCI abort handler
 294  */
 295 static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 296 {
 297         u32 isr, status;
 298
 299         isr = *PCI_ISR;
 300         local_read_config(PCI_STATUS, 2, &status);
 301         pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
 302                 "status = %#x\n", addr, isr, status);
 303
 304         /* make sure the Master Abort bit is reset */
 305         *PCI_ISR = PCI_ISR_PFE;
 306         status |= PCI_STATUS_REC_MASTER_ABORT;
 307         local_write_config(PCI_STATUS, 2, status);
 308
 309         /*
 310          * If it was an imprecise abort, then we need to correct the
 311          * return address to be _after_ the instruction.
 312          */
 313         if (fsr & (1 << 10))
 314                 regs->ARM_pc += 4;
 315
 316         return 0;
 317 }
 318
 319
 320 static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
 321 {
 322         return (dma_addr + size) >= SZ_64M;
 323 }
 324
 325 /*
 326  * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
 327  */
 328 static int ixp4xx_pci_platform_notify(struct device *dev)
 329 {
 330         if(dev->bus == &pci_bus_type) {
 331                 *dev->dma_mask =  SZ_64M - 1;
 332                 dev->coherent_dma_mask = SZ_64M - 1;
 333                 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
 334         }
 335         return 0;
 336 }
 337
 338 static int ixp4xx_pci_platform_notify_remove(struct device *dev)
 339 {
 340         if(dev->bus == &pci_bus_type) {
 341                 dmabounce_unregister_dev(dev);
 342         }
 343         return 0;
 344 }
 345
 346 void __init ixp4xx_pci_preinit(void)
 347 {
 348         unsigned long cpuid = read_cpuid_id();
 349
 350 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
 351         pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
 352 #else
 353         pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
 354 #endif
 355         /*
 356          * Determine which PCI read method to use.
 357          * Rev 0 IXP425 requires workaround.
 358          */
 359         if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
 360                 printk("PCI: IXP42x A0 silicon detected - "
 361                         "PCI Non-Prefetch Workaround Enabled\n");
 362                 ixp4xx_pci_read = ixp4xx_pci_read_errata;
 363         } else
 364                 ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
 365
 366
 367         /* hook in our fault handler for PCI errors */
 368         hook_fault_code(16+6, abort_handler, SIGBUS, 0,
 369                         "imprecise external abort");
 370
 371         pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
 372
 373         /*
 374          * We use identity AHB->PCI address translation
 375          * in the 0x48000000 to 0x4bffffff address space
 376          */
 377         *PCI_PCIMEMBASE = 0x48494A4B;
 378
 379         /*
 380          * We also use identity PCI->AHB address translation
 381          * in 4 16MB BARs that begin at the physical memory start
 382          */
 383         *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
 384                 ((PHYS_OFFSET & 0xFF000000) >> 8) +
 385                 ((PHYS_OFFSET & 0xFF000000) >> 16) +
 386                 ((PHYS_OFFSET & 0xFF000000) >> 24) +
 387                 0x00010203;
 388
 389         if (*PCI_CSR & PCI_CSR_HOST) {
 390                 printk("PCI: IXP4xx is host\n");
 391
 392                 pr_debug("setup BARs in controller\n");
 393
 394                 /*
 395                  * We configure the PCI inbound memory windows to be
 396                  * 1:1 mapped to SDRAM
 397                  */
 398                 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
 399                 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
 400                 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
 401                 local_write_config(PCI_BASE_ADDRESS_3, 4,
 402                                         PHYS_OFFSET + SZ_32M + SZ_16M);
 403
 404                 /*
 405                  * Enable CSR window at 64 MiB to allow PCI masters
 406                  * to continue prefetching past 64 MiB boundary.
 407                  */
 408                 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
 409
 410                 /*
 411                  * Enable the IO window to be way up high, at 0xfffffc00
 412                  */
 413                 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
 414         } else {
 415                 printk("PCI: IXP4xx is target - No bus scan performed\n");
 416         }
 417
 418         printk("PCI: IXP4xx Using %s access for memory space\n",
 419 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 420                         "direct"
 421 #else
 422                         "indirect"
 423 #endif
 424                 );
 425
 426         pr_debug("clear error bits in ISR\n");
 427         *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
 428
 429         /*
 430          * Set Initialize Complete in PCI Control Register: allow IXP4XX to
 431          * respond to PCI configuration cycles. Specify that the AHB bus is
 432          * operating in big endian mode. Set up byte lane swapping between
 433          * little-endian PCI and the big-endian AHB bus
 434          */
 435 #ifdef __ARMEB__
 436         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
 437 #else
 438         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
 439 #endif
 440
 441         pr_debug("DONE\n");
 442 }
 443
 444 int ixp4xx_setup(int nr, struct pci_sys_data *sys)
 445 {
 446         struct resource *res;
 447
 448         if (nr >= 1)
 449                 return 0;
 450
 451         res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
 452         if (res == NULL) {
 453                 /*
 454                  * If we're out of memory this early, something is wrong,
 455                  * so we might as well catch it here.
 456                  */
 457                 panic("PCI: unable to allocate resources?\n");
 458         }
 459
 460         local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 461
 462         res[0].name = "PCI I/O Space";
 463         res[0].start = 0x00000000;
 464         res[0].end = 0x0000ffff;
 465         res[0].flags = IORESOURCE_IO;
 466
 467         res[1].name = "PCI Memory Space";
 468         res[1].start = PCIBIOS_MIN_MEM;
 469         res[1].end = PCIBIOS_MAX_MEM;
 470         res[1].flags = IORESOURCE_MEM;
 471
 472         request_resource(&ioport_resource, &res[0]);
 473         request_resource(&iomem_resource, &res[1]);
 474
 475         pci_add_resource(&sys->resources, &res[0]);
 476         pci_add_resource(&sys->resources, &res[1]);
 477
 478         platform_notify = ixp4xx_pci_platform_notify;
 479         platform_notify_remove = ixp4xx_pci_platform_notify_remove;
 480
 481         return 1;
 482 }
 483
 484 struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
 485 {
 486         return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
 487                                  &sys->resources);
 488 }
 489
 490 int dma_set_coherent_mask(struct device *dev, u64 mask)
 491 {
 492         if (mask >= SZ_64M - 1)
 493                 return 0;
 494
 495         return -EIO;
 496 }
 497
 498 EXPORT_SYMBOL(ixp4xx_pci_read);
 499 EXPORT_SYMBOL(ixp4xx_pci_write);
 500 EXPORT_SYMBOL(dma_set_coherent_mask);