spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-mmp / brownstone.c
blobd839fe6421e69654468a3e3aaa22002cdb142076
1 /*
2 * linux/arch/arm/mach-mmp/brownstone.c
4 * Support for the Marvell Brownstone Development Platform.
6 * Copyright (C) 2009-2010 Marvell International Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * publishhed by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/regulator/machine.h>
18 #include <linux/regulator/max8649.h>
19 #include <linux/regulator/fixed.h>
20 #include <linux/mfd/max8925.h>
22 #include <asm/mach-types.h>
23 #include <asm/mach/arch.h>
24 #include <mach/addr-map.h>
25 #include <mach/mfp-mmp2.h>
26 #include <mach/mmp2.h>
27 #include <mach/irqs.h>
29 #include "common.h"
31 #define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40)
33 #define GPIO_5V_ENABLE (89)
35 static unsigned long brownstone_pin_config[] __initdata = {
36 /* UART1 */
37 GPIO29_UART1_RXD,
38 GPIO30_UART1_TXD,
40 /* UART3 */
41 GPIO51_UART3_RXD,
42 GPIO52_UART3_TXD,
44 /* DFI */
45 GPIO168_DFI_D0,
46 GPIO167_DFI_D1,
47 GPIO166_DFI_D2,
48 GPIO165_DFI_D3,
49 GPIO107_DFI_D4,
50 GPIO106_DFI_D5,
51 GPIO105_DFI_D6,
52 GPIO104_DFI_D7,
53 GPIO111_DFI_D8,
54 GPIO164_DFI_D9,
55 GPIO163_DFI_D10,
56 GPIO162_DFI_D11,
57 GPIO161_DFI_D12,
58 GPIO110_DFI_D13,
59 GPIO109_DFI_D14,
60 GPIO108_DFI_D15,
61 GPIO143_ND_nCS0,
62 GPIO144_ND_nCS1,
63 GPIO147_ND_nWE,
64 GPIO148_ND_nRE,
65 GPIO150_ND_ALE,
66 GPIO149_ND_CLE,
67 GPIO112_ND_RDY0,
68 GPIO160_ND_RDY1,
70 /* PMIC */
71 PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
73 /* MMC0 */
74 GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
75 GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
76 GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
77 GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
78 GPIO136_MMC1_CMD | MFP_PULL_HIGH,
79 GPIO139_MMC1_CLK,
80 GPIO140_MMC1_CD | MFP_PULL_LOW,
81 GPIO141_MMC1_WP | MFP_PULL_LOW,
83 /* MMC1 */
84 GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
85 GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
86 GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
87 GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
88 GPIO41_MMC2_CMD | MFP_PULL_HIGH,
89 GPIO42_MMC2_CLK,
91 /* MMC2 */
92 GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
93 GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
94 GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
95 GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
96 GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
97 GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
98 GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
99 GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
100 GPIO112_MMC3_CMD | MFP_PULL_HIGH,
101 GPIO151_MMC3_CLK,
103 /* 5V regulator */
104 GPIO89_GPIO,
107 static struct regulator_consumer_supply max8649_supply[] = {
108 REGULATOR_SUPPLY("vcc_core", NULL),
111 static struct regulator_init_data max8649_init_data = {
112 .constraints = {
113 .name = "vcc_core range",
114 .min_uV = 1150000,
115 .max_uV = 1280000,
116 .always_on = 1,
117 .boot_on = 1,
118 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
120 .num_consumer_supplies = 1,
121 .consumer_supplies = &max8649_supply[0],
124 static struct max8649_platform_data brownstone_max8649_info = {
125 .mode = 2, /* VID1 = 1, VID0 = 0 */
126 .extclk = 0,
127 .ramp_timing = MAX8649_RAMP_32MV,
128 .regulator = &max8649_init_data,
131 static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
132 REGULATOR_SUPPLY("v_5vp", NULL),
135 static struct regulator_init_data brownstone_v_5vp_data = {
136 .constraints = {
137 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
139 .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies),
140 .consumer_supplies = brownstone_v_5vp_supplies,
143 static struct fixed_voltage_config brownstone_v_5vp = {
144 .supply_name = "v_5vp",
145 .microvolts = 5000000,
146 .gpio = GPIO_5V_ENABLE,
147 .enable_high = 1,
148 .enabled_at_boot = 1,
149 .init_data = &brownstone_v_5vp_data,
152 static struct platform_device brownstone_v_5vp_device = {
153 .name = "reg-fixed-voltage",
154 .id = 1,
155 .dev = {
156 .platform_data = &brownstone_v_5vp,
160 static struct max8925_platform_data brownstone_max8925_info = {
161 .irq_base = IRQ_BOARD_START,
164 static struct i2c_board_info brownstone_twsi1_info[] = {
165 [0] = {
166 .type = "max8649",
167 .addr = 0x60,
168 .platform_data = &brownstone_max8649_info,
170 [1] = {
171 .type = "max8925",
172 .addr = 0x3c,
173 .irq = IRQ_MMP2_PMIC,
174 .platform_data = &brownstone_max8925_info,
178 static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
179 .clk_delay_cycles = 0x1f,
182 static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
183 .clk_delay_cycles = 0x1f,
184 .flags = PXA_FLAG_CARD_PERMANENT
185 | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
188 static struct sram_platdata mmp2_asram_platdata = {
189 .pool_name = "asram",
190 .granularity = SRAM_GRANULARITY,
193 static struct sram_platdata mmp2_isram_platdata = {
194 .pool_name = "isram",
195 .granularity = SRAM_GRANULARITY,
198 static void __init brownstone_init(void)
200 mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
202 /* on-chip devices */
203 mmp2_add_uart(1);
204 mmp2_add_uart(3);
205 platform_device_register(&mmp2_device_gpio);
206 mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
207 mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
208 mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
209 mmp2_add_asram(&mmp2_asram_platdata);
210 mmp2_add_isram(&mmp2_isram_platdata);
212 /* enable 5v regulator */
213 platform_device_register(&brownstone_v_5vp_device);
216 MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
217 /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
218 .map_io = mmp_map_io,
219 .nr_irqs = BROWNSTONE_NR_IRQS,
220 .init_irq = mmp2_init_irq,
221 .timer = &mmp2_timer,
222 .init_machine = brownstone_init,
223 .restart = mmp_restart,
224 MACHINE_END