1 /* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
19 #include <linux/of_address.h>
20 #include <linux/of_platform.h>
21 #include <linux/memblock.h>
23 #include <asm/mach-types.h>
24 #include <asm/mach/arch.h>
25 #include <asm/hardware/gic.h>
26 #include <asm/setup.h>
28 #include <mach/board.h>
29 #include <mach/msm_iomap.h>
31 static void __init
msm8x60_fixup(struct tag
*tag
, char **cmdline
,
34 for (; tag
->hdr
.size
; tag
= tag_next(tag
))
35 if (tag
->hdr
.tag
== ATAG_MEM
&&
36 tag
->u
.mem
.start
== 0x40200000) {
37 tag
->u
.mem
.start
= 0x40000000;
38 tag
->u
.mem
.size
+= SZ_2M
;
42 static void __init
msm8x60_reserve(void)
44 memblock_remove(0x40000000, SZ_2M
);
47 static void __init
msm8x60_map_io(void)
52 static void __init
msm8x60_init_irq(void)
54 gic_init(0, GIC_PPI_START
, MSM_QGIC_DIST_BASE
,
55 (void *)MSM_QGIC_CPU_BASE
);
57 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
58 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE
+ GIC_DIST_CONFIG
+ 4);
60 /* RUMI does not adhere to GIC spec by enabling STIs by default.
61 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
63 if (!machine_is_msm8x60_sim())
64 writel(0x0000FFFF, MSM_QGIC_DIST_BASE
+ GIC_DIST_ENABLE_SET
);
67 static void __init
msm8x60_init(void)
72 static struct of_dev_auxdata msm_auxdata_lookup
[] __initdata
= {
76 static struct of_device_id msm_dt_gic_match
[] __initdata
= {
77 { .compatible
= "qcom,msm-8660-qgic", },
81 static void __init
msm8x60_dt_init(void)
83 struct device_node
*node
;
85 node
= of_find_matching_node_by_address(NULL
, msm_dt_gic_match
,
86 MSM8X60_QGIC_DIST_PHYS
);
88 irq_domain_add_simple(node
, GIC_SPI_START
);
90 if (of_machine_is_compatible("qcom,msm8660-surf")) {
91 printk(KERN_INFO
"Init surf UART registers\n");
92 msm8x60_init_uart12dm();
95 of_platform_populate(NULL
, of_default_bus_match_table
,
96 msm_auxdata_lookup
, NULL
);
99 static const char *msm8x60_fluid_match
[] __initdata
= {
100 "qcom,msm8660-fluid",
104 #endif /* CONFIG_OF */
106 MACHINE_START(MSM8X60_RUMI3
, "QCT MSM8X60 RUMI3")
107 .fixup
= msm8x60_fixup
,
108 .reserve
= msm8x60_reserve
,
109 .map_io
= msm8x60_map_io
,
110 .init_irq
= msm8x60_init_irq
,
111 .handle_irq
= gic_handle_irq
,
112 .init_machine
= msm8x60_init
,
116 MACHINE_START(MSM8X60_SURF
, "QCT MSM8X60 SURF")
117 .fixup
= msm8x60_fixup
,
118 .reserve
= msm8x60_reserve
,
119 .map_io
= msm8x60_map_io
,
120 .init_irq
= msm8x60_init_irq
,
121 .handle_irq
= gic_handle_irq
,
122 .init_machine
= msm8x60_init
,
126 MACHINE_START(MSM8X60_SIM
, "QCT MSM8X60 SIMULATOR")
127 .fixup
= msm8x60_fixup
,
128 .reserve
= msm8x60_reserve
,
129 .map_io
= msm8x60_map_io
,
130 .init_irq
= msm8x60_init_irq
,
131 .handle_irq
= gic_handle_irq
,
132 .init_machine
= msm8x60_init
,
136 MACHINE_START(MSM8X60_FFA
, "QCT MSM8X60 FFA")
137 .fixup
= msm8x60_fixup
,
138 .reserve
= msm8x60_reserve
,
139 .map_io
= msm8x60_map_io
,
140 .init_irq
= msm8x60_init_irq
,
141 .handle_irq
= gic_handle_irq
,
142 .init_machine
= msm8x60_init
,
147 /* TODO: General device tree support for all MSM. */
148 DT_MACHINE_START(MSM_DT
, "Qualcomm MSM (Flattened Device Tree)")
149 .map_io
= msm8x60_map_io
,
150 .init_irq
= msm8x60_init_irq
,
151 .init_machine
= msm8x60_dt_init
,
153 .dt_compat
= msm8x60_fluid_match
,
155 #endif /* CONFIG_OF */