spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-msm / headsmp.S
blobbcd5af223deabaf48451bf3a4d67cea23c82566e
1 /*
2  *  linux/arch/arm/mach-realview/headsmp.S
3  *
4  *  Copyright (c) 2003 ARM Limited
5  *  All Rights Reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/linkage.h>
12 #include <linux/init.h>
14         __CPUINIT
17  * MSM specific entry point for secondary CPUs.  This provides
18  * a "holding pen" into which all secondary cores are held until we're
19  * ready for them to initialise.
20  */
21 ENTRY(msm_secondary_startup)
22         mrc     p15, 0, r0, c0, c0, 5
23         and     r0, r0, #15
24         adr     r4, 1f
25         ldmia   r4, {r5, r6}
26         sub     r4, r4, r5
27         add     r6, r6, r4
28 pen:    ldr     r7, [r6]
29         cmp     r7, r0
30         bne     pen
32         /*
33          * we've been released from the holding pen: secondary_stack
34          * should now contain the SVC stack for this core
35          */
36         b       secondary_startup
37 ENDPROC(msm_secondary_startup)
39         .align
40 1:      .long   .
41         .long   pen_release