spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-mv78xx0 / include / mach / entry-macro.S
blob66ae2d29e7731ccc9c3b14685ed92c42abc5d4fa
1 /*
2  * arch/arm/mach-mv78xx0/include/mach/entry-macro.S
3  *
4  * Low-level IRQ helper macros for Marvell MV78xx0 platforms
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2.  This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
11 #include <mach/bridge-regs.h>
13         .macro  disable_fiq
14         .endm
16         .macro  arch_ret_to_user, tmp1, tmp2
17         .endm
19         .macro  get_irqnr_preamble, base, tmp
20         ldr     \base, =IRQ_VIRT_BASE
21         .endm
23         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
24         @ check low interrupts
25         ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26         ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
27         mov     \irqnr, #31
28         ands    \irqstat, \irqstat, \tmp
29         bne     1001f
31         @ if no low interrupts set, check high interrupts
32         ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
33         ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
34         mov     \irqnr, #63
35         ands    \irqstat, \irqstat, \tmp
36         bne     1001f
38         @ if no high interrupts set, check error interrupts
39         ldr     \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
40         ldr     \tmp, [\base, #IRQ_MASK_ERR_OFF]
41         mov     \irqnr, #95
42         ands    \irqstat, \irqstat, \tmp
44         @ find first active interrupt source
45 1001:   clzne   \irqstat, \irqstat
46         subne   \irqnr, \irqnr, \irqstat
47         .endm