spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-omap1 / gpio15xx.c
blob399da4ce017bfb39d9134e869002710da6f28e20
1 /*
2 * OMAP15xx specific gpio init
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * Author:
7 * Charulatha V <charu@ti.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/gpio.h>
21 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
22 #define OMAP1510_GPIO_BASE 0xFFFCE000
24 /* gpio1 */
25 static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
27 .start = OMAP1_MPUIO_VBASE,
28 .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
29 .flags = IORESOURCE_MEM,
32 .start = INT_MPUIO,
33 .flags = IORESOURCE_IRQ,
37 static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
38 .revision = USHRT_MAX,
39 .direction = OMAP_MPUIO_IO_CNTL,
40 .datain = OMAP_MPUIO_INPUT_LATCH,
41 .dataout = OMAP_MPUIO_OUTPUT,
42 .irqstatus = OMAP_MPUIO_GPIO_INT,
43 .irqenable = OMAP_MPUIO_GPIO_MASKIT,
44 .irqenable_inv = true,
47 static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
48 .virtual_irq_start = IH_MPUIO_BASE,
49 .bank_type = METHOD_MPUIO,
50 .bank_width = 16,
51 .bank_stride = 1,
52 .regs = &omap15xx_mpuio_regs,
55 static struct platform_device omap15xx_mpu_gpio = {
56 .name = "omap_gpio",
57 .id = 0,
58 .dev = {
59 .platform_data = &omap15xx_mpu_gpio_config,
61 .num_resources = ARRAY_SIZE(omap15xx_mpu_gpio_resources),
62 .resource = omap15xx_mpu_gpio_resources,
65 /* gpio2 */
66 static struct __initdata resource omap15xx_gpio_resources[] = {
68 .start = OMAP1510_GPIO_BASE,
69 .end = OMAP1510_GPIO_BASE + SZ_2K - 1,
70 .flags = IORESOURCE_MEM,
73 .start = INT_GPIO_BANK1,
74 .flags = IORESOURCE_IRQ,
78 static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
79 .revision = USHRT_MAX,
80 .direction = OMAP1510_GPIO_DIR_CONTROL,
81 .datain = OMAP1510_GPIO_DATA_INPUT,
82 .dataout = OMAP1510_GPIO_DATA_OUTPUT,
83 .irqstatus = OMAP1510_GPIO_INT_STATUS,
84 .irqenable = OMAP1510_GPIO_INT_MASK,
85 .irqenable_inv = true,
88 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
89 .virtual_irq_start = IH_GPIO_BASE,
90 .bank_type = METHOD_GPIO_1510,
91 .bank_width = 16,
92 .regs = &omap15xx_gpio_regs,
95 static struct platform_device omap15xx_gpio = {
96 .name = "omap_gpio",
97 .id = 1,
98 .dev = {
99 .platform_data = &omap15xx_gpio_config,
101 .num_resources = ARRAY_SIZE(omap15xx_gpio_resources),
102 .resource = omap15xx_gpio_resources,
106 * omap15xx_gpio_init needs to be done before
107 * machine_init functions access gpio APIs.
108 * Hence omap15xx_gpio_init is a postcore_initcall.
110 static int __init omap15xx_gpio_init(void)
112 if (!cpu_is_omap15xx())
113 return -EINVAL;
115 platform_device_register(&omap15xx_mpu_gpio);
116 platform_device_register(&omap15xx_gpio);
118 gpio_bank_count = 2;
119 return 0;
121 postcore_initcall(omap15xx_gpio_init);