spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-omap1 / include / mach / entry-macro.S
blobbfb4fb1d7382018e24b4dfb561bbf7cb6d92967d
1 /*
2  * arch/arm/mach-omap1/include/mach/entry-macro.S
3  *
4  * Low-level IRQ helper macros for OMAP-based platforms
5  *
6  * Copyright (C) 2009 Texas Instruments
7  *
8  * This file is licensed under  the terms of the GNU General Public
9  * License version 2. This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 #include <mach/hardware.h>
13 #include <mach/io.h>
14 #include <mach/irqs.h>
15 #include <asm/hardware/gic.h>
17                 .macro  disable_fiq
18                 .endm
20                 .macro  get_irqnr_preamble, base, tmp
21                 .endm
23                 .macro  arch_ret_to_user, tmp1, tmp2
24                 .endm
26                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
27                 ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
28                 ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
29                 ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
30                 mov     \irqstat, #0xffffffff
31                 bic     \tmp, \irqstat, \tmp
32                 tst     \irqnr, \tmp
33                 beq     1510f
35                 ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
36                 ldr     \tmp, =omap_irq_flags   @ irq flags address
37                 ldr     \tmp, [\tmp, #0]        @ irq flags value
38                 cmp     \irqnr, #0
39                 ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
40                 cmpeq   \irqnr, \tmp
41                 ldreq   \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
42                 ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
43                 addeqs  \irqnr, \irqnr, #32
44 1510:
45                 .endm