spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-omap2 / omap-iommu.c
blobac49384d028521deceb8e11355b46fbd4a2ec1b9
1 /*
2 * omap iommu: omap device registration
4 * Copyright (C) 2008-2009 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <plat/iommu.h>
17 #include <plat/irqs.h>
19 struct iommu_device {
20 resource_size_t base;
21 int irq;
22 struct iommu_platform_data pdata;
23 struct resource res[2];
25 static struct iommu_device *devices;
26 static int num_iommu_devices;
28 #ifdef CONFIG_ARCH_OMAP3
29 static struct iommu_device omap3_devices[] = {
31 .base = 0x480bd400,
32 .irq = 24,
33 .pdata = {
34 .name = "isp",
35 .nr_tlb_entries = 8,
36 .clk_name = "cam_ick",
37 .da_start = 0x0,
38 .da_end = 0xFFFFF000,
41 #if defined(CONFIG_OMAP_IOMMU_IVA2)
43 .base = 0x5d000000,
44 .irq = 28,
45 .pdata = {
46 .name = "iva2",
47 .nr_tlb_entries = 32,
48 .clk_name = "iva2_ck",
49 .da_start = 0x11000000,
50 .da_end = 0xFFFFF000,
53 #endif
55 #define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
56 static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
57 #else
58 #define omap3_devices NULL
59 #define NR_OMAP3_IOMMU_DEVICES 0
60 #define omap3_iommu_pdev NULL
61 #endif
63 #ifdef CONFIG_ARCH_OMAP4
64 static struct iommu_device omap4_devices[] = {
66 .base = OMAP4_MMU1_BASE,
67 .irq = OMAP44XX_IRQ_DUCATI_MMU,
68 .pdata = {
69 .name = "ducati",
70 .nr_tlb_entries = 32,
71 .clk_name = "ipu_fck",
72 .da_start = 0x0,
73 .da_end = 0xFFFFF000,
76 #if defined(CONFIG_MPU_TESLA_IOMMU)
78 .base = OMAP4_MMU2_BASE,
79 .irq = INT_44XX_DSP_MMU,
80 .pdata = {
81 .name = "tesla",
82 .nr_tlb_entries = 32,
83 .clk_name = "tesla_ick",
84 .da_start = 0x0,
85 .da_end = 0xFFFFF000,
88 #endif
90 #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
91 static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
92 #else
93 #define omap4_devices NULL
94 #define NR_OMAP4_IOMMU_DEVICES 0
95 #define omap4_iommu_pdev NULL
96 #endif
98 static struct platform_device **omap_iommu_pdev;
100 static int __init omap_iommu_init(void)
102 int i, err;
103 struct resource res[] = {
104 { .flags = IORESOURCE_MEM },
105 { .flags = IORESOURCE_IRQ },
108 if (cpu_is_omap34xx()) {
109 devices = omap3_devices;
110 omap_iommu_pdev = omap3_iommu_pdev;
111 num_iommu_devices = NR_OMAP3_IOMMU_DEVICES;
112 } else if (cpu_is_omap44xx()) {
113 devices = omap4_devices;
114 omap_iommu_pdev = omap4_iommu_pdev;
115 num_iommu_devices = NR_OMAP4_IOMMU_DEVICES;
116 } else
117 return -ENODEV;
119 for (i = 0; i < num_iommu_devices; i++) {
120 struct platform_device *pdev;
121 const struct iommu_device *d = &devices[i];
123 pdev = platform_device_alloc("omap-iommu", i);
124 if (!pdev) {
125 err = -ENOMEM;
126 goto err_out;
129 res[0].start = d->base;
130 res[0].end = d->base + MMU_REG_SIZE - 1;
131 res[1].start = res[1].end = d->irq;
133 err = platform_device_add_resources(pdev, res,
134 ARRAY_SIZE(res));
135 if (err)
136 goto err_out;
137 err = platform_device_add_data(pdev, &d->pdata,
138 sizeof(d->pdata));
139 if (err)
140 goto err_out;
141 err = platform_device_add(pdev);
142 if (err)
143 goto err_out;
144 omap_iommu_pdev[i] = pdev;
146 return 0;
148 err_out:
149 while (i--)
150 platform_device_put(omap_iommu_pdev[i]);
151 return err;
153 /* must be ready before omap3isp is probed */
154 subsys_initcall(omap_iommu_init);
156 static void __exit omap_iommu_exit(void)
158 int i;
160 for (i = 0; i < num_iommu_devices; i++)
161 platform_device_unregister(omap_iommu_pdev[i]);
163 module_exit(omap_iommu_exit);
165 MODULE_AUTHOR("Hiroshi DOYU");
166 MODULE_DESCRIPTION("omap iommu: omap device registration");
167 MODULE_LICENSE("GPL v2");