arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39
  40 #include <asm/mach/time.h>
  41 #include <plat/dmtimer.h>
  42 #include <asm/localtimer.h>
  43 #include <asm/sched_clock.h>
  44 #include "common.h"
  45 #include <plat/omap_hwmod.h>
  46 #include <plat/omap_device.h>
  47 #include <plat/omap-pm.h>
  48
  49 #include "powerdomain.h"
  50
  51 /* Parent clocks, eventually these will come from the clock framework */
  52
  53 #define OMAP2_MPU_SOURCE        "sys_ck"
  54 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  55 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  56 #define OMAP2_32K_SOURCE        "func_32k_ck"
  57 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  58 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  59
  60 #ifdef CONFIG_OMAP_32K_TIMER
  61 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  62 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  63 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  64 #define OMAP3_SECURE_TIMER      12
  65 #else
  66 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  67 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  68 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  69 #define OMAP3_SECURE_TIMER      1
  70 #endif
  71
  72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  73 #define MAX_GPTIMER_ID          12
  74
  75 static u32 sys_timer_reserved;
  76
  77 /* Clockevent code */
  78
  79 static struct omap_dm_timer clkev;
  80 static struct clock_event_device clockevent_gpt;
  81
  82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  83 {
  84         struct clock_event_device *evt = &clockevent_gpt;
  85
  86         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  87
  88         evt->event_handler(evt);
  89         return IRQ_HANDLED;
  90 }
  91
  92 static struct irqaction omap2_gp_timer_irq = {
  93         .name           = "gp timer",
  94         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  95         .handler        = omap2_gp_timer_interrupt,
  96 };
  97
  98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  99                                          struct clock_event_device *evt)
 100 {
 101         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 102                                                 0xffffffff - cycles, 1);
 103
 104         return 0;
 105 }
 106
 107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 108                                     struct clock_event_device *evt)
 109 {
 110         u32 period;
 111
 112         __omap_dm_timer_stop(&clkev, 1, clkev.rate);
 113
 114         switch (mode) {
 115         case CLOCK_EVT_MODE_PERIODIC:
 116                 period = clkev.rate / HZ;
 117                 period -= 1;
 118                 /* Looks like we need to first set the load value separately */
 119                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 120                                         0xffffffff - period, 1);
 121                 __omap_dm_timer_load_start(&clkev,
 122                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 123                                                 0xffffffff - period, 1);
 124                 break;
 125         case CLOCK_EVT_MODE_ONESHOT:
 126                 break;
 127         case CLOCK_EVT_MODE_UNUSED:
 128         case CLOCK_EVT_MODE_SHUTDOWN:
 129         case CLOCK_EVT_MODE_RESUME:
 130                 break;
 131         }
 132 }
 133
 134 static struct clock_event_device clockevent_gpt = {
 135         .name           = "gp timer",
 136         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 137         .shift          = 32,
 138         .set_next_event = omap2_gp_timer_set_next_event,
 139         .set_mode       = omap2_gp_timer_set_mode,
 140 };
 141
 142 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 143                                                 int gptimer_id,
 144                                                 const char *fck_source)
 145 {
 146         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 147         struct omap_hwmod *oh;
 148         size_t size;
 149         int res = 0;
 150
 151         sprintf(name, "timer%d", gptimer_id);
 152         omap_hwmod_setup_one(name);
 153         oh = omap_hwmod_lookup(name);
 154         if (!oh)
 155                 return -ENODEV;
 156
 157         timer->irq = oh->mpu_irqs[0].irq;
 158         timer->phys_base = oh->slaves[0]->addr->pa_start;
 159         size = oh->slaves[0]->addr->pa_end - timer->phys_base;
 160
 161         /* Static mapping, never released */
 162         timer->io_base = ioremap(timer->phys_base, size);
 163         if (!timer->io_base)
 164                 return -ENXIO;
 165
 166         /* After the dmtimer is using hwmod these clocks won't be needed */
 167         sprintf(name, "gpt%d_fck", gptimer_id);
 168         timer->fclk = clk_get(NULL, name);
 169         if (IS_ERR(timer->fclk))
 170                 return -ENODEV;
 171
 172         sprintf(name, "gpt%d_ick", gptimer_id);
 173         timer->iclk = clk_get(NULL, name);
 174         if (IS_ERR(timer->iclk)) {
 175                 clk_put(timer->fclk);
 176                 return -ENODEV;
 177         }
 178
 179         omap_hwmod_enable(oh);
 180
 181         sys_timer_reserved |= (1 << (gptimer_id - 1));
 182
 183         if (gptimer_id != 12) {
 184                 struct clk *src;
 185
 186                 src = clk_get(NULL, fck_source);
 187                 if (IS_ERR(src)) {
 188                         res = -EINVAL;
 189                 } else {
 190                         res = __omap_dm_timer_set_source(timer->fclk, src);
 191                         if (IS_ERR_VALUE(res))
 192                                 pr_warning("%s: timer%i cannot set source\n",
 193                                                 __func__, gptimer_id);
 194                         clk_put(src);
 195                 }
 196         }
 197         __omap_dm_timer_init_regs(timer);
 198         __omap_dm_timer_reset(timer, 1, 1);
 199         timer->posted = 1;
 200
 201         timer->rate = clk_get_rate(timer->fclk);
 202
 203         timer->reserved = 1;
 204
 205         return res;
 206 }
 207
 208 static void __init omap2_gp_clockevent_init(int gptimer_id,
 209                                                 const char *fck_source)
 210 {
 211         int res;
 212
 213         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
 214         BUG_ON(res);
 215
 216         omap2_gp_timer_irq.dev_id = (void *)&clkev;
 217         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 218
 219         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 220
 221         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 222                                      clockevent_gpt.shift);
 223         clockevent_gpt.max_delta_ns =
 224                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 225         clockevent_gpt.min_delta_ns =
 226                 clockevent_delta2ns(3, &clockevent_gpt);
 227                 /* Timer internal resynch latency. */
 228
 229         clockevent_gpt.cpumask = cpumask_of(0);
 230         clockevents_register_device(&clockevent_gpt);
 231
 232         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 233                 gptimer_id, clkev.rate);
 234 }
 235
 236 /* Clocksource code */
 237
 238 #ifdef CONFIG_OMAP_32K_TIMER
 239 /*
 240  * When 32k-timer is enabled, don't use GPTimer for clocksource
 241  * instead, just leave default clocksource which uses the 32k
 242  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 243  */
 244
 245 static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
 246 {
 247         omap_init_clocksource_32k();
 248 }
 249
 250 #else
 251
 252 static struct omap_dm_timer clksrc;
 253
 254 /*
 255  * clocksource
 256  */
 257 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 258 {
 259         return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 260 }
 261
 262 static struct clocksource clocksource_gpt = {
 263         .name           = "gp timer",
 264         .rating         = 300,
 265         .read           = clocksource_read_cycles,
 266         .mask           = CLOCKSOURCE_MASK(32),
 267         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 268 };
 269
 270 static u32 notrace dmtimer_read_sched_clock(void)
 271 {
 272         if (clksrc.reserved)
 273                 return __omap_dm_timer_read_counter(&clksrc, 1);
 274
 275         return 0;
 276 }
 277
 278 /* Setup free-running counter for clocksource */
 279 static void __init omap2_gp_clocksource_init(int gptimer_id,
 280                                                 const char *fck_source)
 281 {
 282         int res;
 283
 284         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
 285         BUG_ON(res);
 286
 287         pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 288                 gptimer_id, clksrc.rate);
 289
 290         __omap_dm_timer_load_start(&clksrc,
 291                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
 292         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 293
 294         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 295                 pr_err("Could not register clocksource %s\n",
 296                         clocksource_gpt.name);
 297 }
 298 #endif
 299
 300 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
 301                                 clksrc_nr, clksrc_src)                  \
 302 static void __init omap##name##_timer_init(void)                        \
 303 {                                                                       \
 304         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
 305         omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
 306 }
 307
 308 #define OMAP_SYS_TIMER(name)                                            \
 309 struct sys_timer omap##name##_timer = {                                 \
 310         .init   = omap##name##_timer_init,                              \
 311 };
 312
 313 #ifdef CONFIG_ARCH_OMAP2
 314 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
 315 OMAP_SYS_TIMER(2)
 316 #endif
 317
 318 #ifdef CONFIG_ARCH_OMAP3
 319 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
 320 OMAP_SYS_TIMER(3)
 321 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 322                         2, OMAP3_MPU_SOURCE)
 323 OMAP_SYS_TIMER(3_secure)
 324 #endif
 325
 326 #ifdef CONFIG_ARCH_OMAP4
 327 static void __init omap4_timer_init(void)
 328 {
 329 #ifdef CONFIG_LOCAL_TIMERS
 330         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 331         BUG_ON(!twd_base);
 332 #endif
 333         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 334         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
 335 }
 336 OMAP_SYS_TIMER(4)
 337 #endif
 338
 339 /**
 340  * omap2_dm_timer_set_src - change the timer input clock source
 341  * @pdev:       timer platform device pointer
 342  * @source:     array index of parent clock source
 343  */
 344 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
 345 {
 346         int ret;
 347         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 348         struct clk *fclk, *parent;
 349         char *parent_name = NULL;
 350
 351         fclk = clk_get(&pdev->dev, "fck");
 352         if (IS_ERR_OR_NULL(fclk)) {
 353                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
 354                                 __func__, __LINE__);
 355                 return -EINVAL;
 356         }
 357
 358         switch (source) {
 359         case OMAP_TIMER_SRC_SYS_CLK:
 360                 parent_name = "sys_ck";
 361                 break;
 362
 363         case OMAP_TIMER_SRC_32_KHZ:
 364                 parent_name = "32k_ck";
 365                 break;
 366
 367         case OMAP_TIMER_SRC_EXT_CLK:
 368                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
 369                         parent_name = "alt_ck";
 370                         break;
 371                 }
 372                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
 373                         __func__, __LINE__);
 374                 clk_put(fclk);
 375                 return -EINVAL;
 376         }
 377
 378         parent = clk_get(&pdev->dev, parent_name);
 379         if (IS_ERR_OR_NULL(parent)) {
 380                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
 381                         __func__, __LINE__, parent_name);
 382                 clk_put(fclk);
 383                 return -EINVAL;
 384         }
 385
 386         ret = clk_set_parent(fclk, parent);
 387         if (IS_ERR_VALUE(ret)) {
 388                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
 389                         __func__, parent_name);
 390                 ret = -EINVAL;
 391         }
 392
 393         clk_put(parent);
 394         clk_put(fclk);
 395
 396         return ret;
 397 }
 398
 399 /**
 400  * omap_timer_init - build and register timer device with an
 401  * associated timer hwmod
 402  * @oh: timer hwmod pointer to be used to build timer device
 403  * @user:       parameter that can be passed from calling hwmod API
 404  *
 405  * Called by omap_hwmod_for_each_by_class to register each of the timer
 406  * devices present in the system. The number of timer devices is known
 407  * by parsing through the hwmod database for a given class name. At the
 408  * end of function call memory is allocated for timer device and it is
 409  * registered to the framework ready to be proved by the driver.
 410  */
 411 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 412 {
 413         int id;
 414         int ret = 0;
 415         char *name = "omap_timer";
 416         struct dmtimer_platform_data *pdata;
 417         struct platform_device *pdev;
 418         struct omap_timer_capability_dev_attr *timer_dev_attr;
 419         struct powerdomain *pwrdm;
 420
 421         pr_debug("%s: %s\n", __func__, oh->name);
 422
 423         /* on secure device, do not register secure timer */
 424         timer_dev_attr = oh->dev_attr;
 425         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 426                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 427                         return ret;
 428
 429         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 430         if (!pdata) {
 431                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 432                 return -ENOMEM;
 433         }
 434
 435         /*
 436          * Extract the IDs from name field in hwmod database
 437          * and use the same for constructing ids' for the
 438          * timer devices. In a way, we are avoiding usage of
 439          * static variable witin the function to do the same.
 440          * CAUTION: We have to be careful and make sure the
 441          * name in hwmod database does not change in which case
 442          * we might either make corresponding change here or
 443          * switch back static variable mechanism.
 444          */
 445         sscanf(oh->name, "timer%2d", &id);
 446
 447         pdata->set_timer_src = omap2_dm_timer_set_src;
 448         pdata->timer_ip_version = oh->class->rev;
 449
 450         /* Mark clocksource and clockevent timers as reserved */
 451         if ((sys_timer_reserved >> (id - 1)) & 0x1)
 452                 pdata->reserved = 1;
 453
 454         pwrdm = omap_hwmod_get_pwrdm(oh);
 455         pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
 456 #ifdef CONFIG_PM
 457         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 458 #endif
 459         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 460                                  NULL, 0, 0);
 461
 462         if (IS_ERR(pdev)) {
 463                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 464                         __func__, name, oh->name);
 465                 ret = -EINVAL;
 466         }
 467
 468         kfree(pdata);
 469
 470         return ret;
 471 }
 472
 473 /**
 474  * omap2_dm_timer_init - top level regular device initialization
 475  *
 476  * Uses dedicated hwmod api to parse through hwmod database for
 477  * given class name and then build and register the timer device.
 478  */
 479 static int __init omap2_dm_timer_init(void)
 480 {
 481         int ret;
 482
 483         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 484         if (unlikely(ret)) {
 485                 pr_err("%s: device registration failed.\n", __func__);
 486                 return -EINVAL;
 487         }
 488
 489         return 0;
 490 }
 491 arch_initcall(omap2_dm_timer_init);