spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-pxa / include / mach / hardware.h
blob8184669dde28116aad82b8854f2346bbac6d00be
1 /*
2 * arch/arm/mach-pxa/include/mach/hardware.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_HARDWARE_H
14 #define __ASM_ARCH_HARDWARE_H
16 #include <mach/addr-map.h>
19 * Workarounds for at least 2 errata so far require this.
20 * The mapping is set in mach-pxa/generic.c.
22 #define UNCACHED_PHYS_0 0xff000000
23 #define UNCACHED_ADDR UNCACHED_PHYS_0
26 * Intel PXA2xx internal register mapping:
28 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
29 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
30 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
31 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
32 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
33 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
34 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
36 * Note that not all PXA2xx chips implement all those addresses, and the
37 * kernel only maps the minimum needed range of this mapping.
39 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
40 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
42 #ifndef __ASSEMBLY__
43 # define IOMEM(x) ((void __iomem *)(x))
44 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
46 /* With indexed regs we don't want to feed the index through io_p2v()
47 especially if it is a variable, otherwise horrible code will result. */
48 # define __REG2(x,y) \
49 (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
51 # define __PREG(x) (io_v2p((u32)&(x)))
53 #else
55 # define IOMEM(x) x
56 # define __REG(x) io_p2v(x)
57 # define __PREG(x) io_v2p(x)
59 #endif
61 #ifndef __ASSEMBLY__
63 #include <asm/cputype.h>
66 * CPU Stepping CPU_ID JTAG_ID
68 * PXA210 B0 0x69052922 0x2926C013
69 * PXA210 B1 0x69052923 0x3926C013
70 * PXA210 B2 0x69052924 0x4926C013
71 * PXA210 C0 0x69052D25 0x5926C013
73 * PXA250 A0 0x69052100 0x09264013
74 * PXA250 A1 0x69052101 0x19264013
75 * PXA250 B0 0x69052902 0x29264013
76 * PXA250 B1 0x69052903 0x39264013
77 * PXA250 B2 0x69052904 0x49264013
78 * PXA250 C0 0x69052D05 0x59264013
80 * PXA255 A0 0x69052D06 0x69264013
82 * PXA26x A0 0x69052903 0x39264013
83 * PXA26x B0 0x69052D05 0x59264013
85 * PXA27x A0 0x69054110 0x09265013
86 * PXA27x A1 0x69054111 0x19265013
87 * PXA27x B0 0x69054112 0x29265013
88 * PXA27x B1 0x69054113 0x39265013
89 * PXA27x C0 0x69054114 0x49265013
90 * PXA27x C5 0x69054117 0x79265013
92 * PXA30x A0 0x69056880 0x0E648013
93 * PXA30x A1 0x69056881 0x1E648013
94 * PXA31x A0 0x69056890 0x0E649013
95 * PXA31x A1 0x69056891 0x1E649013
96 * PXA31x A2 0x69056892 0x2E649013
97 * PXA32x B1 0x69056825 0x5E642013
98 * PXA32x B2 0x69056826 0x6E642013
100 * PXA930 B0 0x69056835 0x5E643013
101 * PXA930 B1 0x69056837 0x7E643013
102 * PXA930 B2 0x69056838 0x8E643013
104 * PXA935 A0 0x56056931 0x1E653013
105 * PXA935 B0 0x56056936 0x6E653013
106 * PXA935 B1 0x56056938 0x8E653013
108 #ifdef CONFIG_PXA25x
109 #define __cpu_is_pxa210(id) \
110 ({ \
111 unsigned int _id = (id) & 0xf3f0; \
112 _id == 0x2120; \
115 #define __cpu_is_pxa250(id) \
116 ({ \
117 unsigned int _id = (id) & 0xf3ff; \
118 _id <= 0x2105; \
121 #define __cpu_is_pxa255(id) \
122 ({ \
123 unsigned int _id = (id) & 0xffff; \
124 _id == 0x2d06; \
127 #define __cpu_is_pxa25x(id) \
128 ({ \
129 unsigned int _id = (id) & 0xf300; \
130 _id == 0x2100; \
132 #else
133 #define __cpu_is_pxa210(id) (0)
134 #define __cpu_is_pxa250(id) (0)
135 #define __cpu_is_pxa255(id) (0)
136 #define __cpu_is_pxa25x(id) (0)
137 #endif
139 #ifdef CONFIG_PXA27x
140 #define __cpu_is_pxa27x(id) \
141 ({ \
142 unsigned int _id = (id) >> 4 & 0xfff; \
143 _id == 0x411; \
145 #else
146 #define __cpu_is_pxa27x(id) (0)
147 #endif
149 #ifdef CONFIG_CPU_PXA300
150 #define __cpu_is_pxa300(id) \
151 ({ \
152 unsigned int _id = (id) >> 4 & 0xfff; \
153 _id == 0x688; \
155 #else
156 #define __cpu_is_pxa300(id) (0)
157 #endif
159 #ifdef CONFIG_CPU_PXA310
160 #define __cpu_is_pxa310(id) \
161 ({ \
162 unsigned int _id = (id) >> 4 & 0xfff; \
163 _id == 0x689; \
165 #else
166 #define __cpu_is_pxa310(id) (0)
167 #endif
169 #ifdef CONFIG_CPU_PXA320
170 #define __cpu_is_pxa320(id) \
171 ({ \
172 unsigned int _id = (id) >> 4 & 0xfff; \
173 _id == 0x603 || _id == 0x682; \
175 #else
176 #define __cpu_is_pxa320(id) (0)
177 #endif
179 #ifdef CONFIG_CPU_PXA930
180 #define __cpu_is_pxa930(id) \
181 ({ \
182 unsigned int _id = (id) >> 4 & 0xfff; \
183 _id == 0x683; \
185 #else
186 #define __cpu_is_pxa930(id) (0)
187 #endif
189 #ifdef CONFIG_CPU_PXA935
190 #define __cpu_is_pxa935(id) \
191 ({ \
192 unsigned int _id = (id) >> 4 & 0xfff; \
193 _id == 0x693; \
195 #else
196 #define __cpu_is_pxa935(id) (0)
197 #endif
199 #ifdef CONFIG_CPU_PXA955
200 #define __cpu_is_pxa955(id) \
201 ({ \
202 unsigned int _id = (id) >> 4 & 0xfff; \
203 _id == 0x581 || _id == 0xc08 \
204 || _id == 0xb76; \
206 #else
207 #define __cpu_is_pxa955(id) (0)
208 #endif
210 #define cpu_is_pxa210() \
211 ({ \
212 __cpu_is_pxa210(read_cpuid_id()); \
215 #define cpu_is_pxa250() \
216 ({ \
217 __cpu_is_pxa250(read_cpuid_id()); \
220 #define cpu_is_pxa255() \
221 ({ \
222 __cpu_is_pxa255(read_cpuid_id()); \
225 #define cpu_is_pxa25x() \
226 ({ \
227 __cpu_is_pxa25x(read_cpuid_id()); \
230 #define cpu_is_pxa27x() \
231 ({ \
232 __cpu_is_pxa27x(read_cpuid_id()); \
235 #define cpu_is_pxa300() \
236 ({ \
237 __cpu_is_pxa300(read_cpuid_id()); \
240 #define cpu_is_pxa310() \
241 ({ \
242 __cpu_is_pxa310(read_cpuid_id()); \
245 #define cpu_is_pxa320() \
246 ({ \
247 __cpu_is_pxa320(read_cpuid_id()); \
250 #define cpu_is_pxa930() \
251 ({ \
252 __cpu_is_pxa930(read_cpuid_id()); \
255 #define cpu_is_pxa935() \
256 ({ \
257 __cpu_is_pxa935(read_cpuid_id()); \
260 #define cpu_is_pxa955() \
261 ({ \
262 __cpu_is_pxa955(read_cpuid_id()); \
267 * CPUID Core Generation Bit
268 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
270 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
271 #define __cpu_is_pxa2xx(id) \
272 ({ \
273 unsigned int _id = (id) >> 13 & 0x7; \
274 _id <= 0x2; \
276 #else
277 #define __cpu_is_pxa2xx(id) (0)
278 #endif
280 #ifdef CONFIG_PXA3xx
281 #define __cpu_is_pxa3xx(id) \
282 ({ \
283 __cpu_is_pxa300(id) \
284 || __cpu_is_pxa310(id) \
285 || __cpu_is_pxa320(id) \
286 || __cpu_is_pxa93x(id); \
288 #else
289 #define __cpu_is_pxa3xx(id) (0)
290 #endif
292 #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
293 #define __cpu_is_pxa93x(id) \
294 ({ \
295 __cpu_is_pxa930(id) \
296 || __cpu_is_pxa935(id); \
298 #else
299 #define __cpu_is_pxa93x(id) (0)
300 #endif
302 #ifdef CONFIG_PXA95x
303 #define __cpu_is_pxa95x(id) \
304 ({ \
305 __cpu_is_pxa955(id); \
307 #else
308 #define __cpu_is_pxa95x(id) (0)
309 #endif
311 #define cpu_is_pxa2xx() \
312 ({ \
313 __cpu_is_pxa2xx(read_cpuid_id()); \
316 #define cpu_is_pxa3xx() \
317 ({ \
318 __cpu_is_pxa3xx(read_cpuid_id()); \
321 #define cpu_is_pxa93x() \
322 ({ \
323 __cpu_is_pxa93x(read_cpuid_id()); \
326 #define cpu_is_pxa95x() \
327 ({ \
328 __cpu_is_pxa95x(read_cpuid_id()); \
332 * return current memory and LCD clock frequency in units of 10kHz
334 extern unsigned int get_memclk_frequency_10khz(void);
336 /* return the clock tick rate of the OS timer */
337 extern unsigned long get_clock_tick_rate(void);
338 #endif
340 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
341 #define ARCH_HAS_DMA_SET_COHERENT_MASK
342 #endif
344 #endif /* _ASM_ARCH_HARDWARE_H */