spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-pxa / include / mach / regs-rtc.h
blobf0e4a589bbe19aa462f312a3693cbe3e8daffe61
1 #ifndef __ASM_MACH_REGS_RTC_H
2 #define __ASM_MACH_REGS_RTC_H
4 #include <mach/hardware.h>
6 /*
7 * Real Time Clock
8 */
10 #define RCNR __REG(0x40900000) /* RTC Count Register */
11 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
12 #define RTSR __REG(0x40900008) /* RTC Status Register */
13 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
14 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
16 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
17 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
18 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
19 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
20 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
21 #define RTSR_AL (1 << 0) /* RTC alarm detected */
23 #endif /* __ASM_MACH_REGS_RTC_H */