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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-pxa / mfp-pxa2xx.c
blob29b62afc6f7ca3d219b4f4498c4b62b3a6fee223
1 /*
2 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
3 *
4 * PXA2xx pin mux configuration support
5 *
6 * The GPIOs on PXA2xx can be configured as one of many alternate
7 * functions, this is by concept samilar to the MFP configuration
8 * on PXA3xx, what's more important, the low power pin state and
9 * wakeup detection are also supported by the same framework.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #include <linux/gpio.h>
16 #include <linux/gpio-pxa.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/syscore_ops.h>
21
22 #include <mach/pxa2xx-regs.h>
23 #include <mach/mfp-pxa2xx.h>
24
25 #include "generic.h"
26
27 #define PGSR(x) __REG2(0x40F00020, (x) << 2)
28 #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
29 #define GAFR_L(x) __GAFR(0, x)
30 #define GAFR_U(x) __GAFR(1, x)
31
32 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
33 #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
34 #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
35
36 #define PWER_WE35 (1 << 24)
37
38 struct gpio_desc {
39 unsigned valid : 1;
40 unsigned can_wakeup : 1;
41 unsigned keypad_gpio : 1;
42 unsigned dir_inverted : 1;
43 unsigned int mask; /* bit mask in PWER or PKWR */
44 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
45 unsigned long config;
46 };
47
48 static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
49
50 static unsigned long gpdr_lpm[4];
51
52 static int __mfp_config_gpio(unsigned gpio, unsigned long c)
53 {
54 unsigned long gafr, mask = GPIO_bit(gpio);
55 int bank = gpio_to_bank(gpio);
56 int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
57 int shft = (gpio & 0xf) << 1;
58 int fn = MFP_AF(c);
59 int is_out = (c & MFP_DIR_OUT) ? 1 : 0;
60
61 if (fn > 3)
62 return -EINVAL;
63
64 /* alternate function and direction at run-time */
65 gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
66 gafr = (gafr & ~(0x3 << shft)) | (fn << shft);
67
68 if (uorl == 0)
69 GAFR_L(bank) = gafr;
70 else
71 GAFR_U(bank) = gafr;
72
73 if (is_out ^ gpio_desc[gpio].dir_inverted)
74 GPDR(gpio) |= mask;
75 else
76 GPDR(gpio) &= ~mask;
77
78 /* alternate function and direction at low power mode */
79 switch (c & MFP_LPM_STATE_MASK) {
80 case MFP_LPM_DRIVE_HIGH:
81 PGSR(bank) |= mask;
82 is_out = 1;
83 break;
84 case MFP_LPM_DRIVE_LOW:
85 PGSR(bank) &= ~mask;
86 is_out = 1;
87 break;
88 case MFP_LPM_INPUT:
89 case MFP_LPM_DEFAULT:
90 break;
91 default:
92 /* warning and fall through, treat as MFP_LPM_DEFAULT */
93 pr_warning("%s: GPIO%d: unsupported low power mode\n",
94 __func__, gpio);
95 break;
96 }
97
98 if (is_out ^ gpio_desc[gpio].dir_inverted)
99 gpdr_lpm[bank] |= mask;
100 else
101 gpdr_lpm[bank] &= ~mask;
102
103 /* give early warning if MFP_LPM_CAN_WAKEUP is set on the
104 * configurations of those pins not able to wakeup
105 */
106 if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
107 pr_warning("%s: GPIO%d unable to wakeup\n",
108 __func__, gpio);
109 return -EINVAL;
110 }
111
112 if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
113 pr_warning("%s: output GPIO%d unable to wakeup\n",
114 __func__, gpio);
115 return -EINVAL;
116 }
117
118 return 0;
119 }
120
121 static inline int __mfp_validate(int mfp)
122 {
123 int gpio = mfp_to_gpio(mfp);
124
125 if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) {
126 pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio);
127 return -1;
128 }
129
130 return gpio;
131 }
132
133 void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
134 {
135 unsigned long flags;
136 unsigned long *c;
137 int i, gpio;
138
139 for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
140
141 gpio = __mfp_validate(MFP_PIN(*c));
142 if (gpio < 0)
143 continue;
144
145 local_irq_save(flags);
146
147 gpio_desc[gpio].config = *c;
148 __mfp_config_gpio(gpio, *c);
149
150 local_irq_restore(flags);
151 }
152 }
153
154 void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
155 {
156 unsigned long flags, c;
157 int gpio;
158
159 gpio = __mfp_validate(mfp);
160 if (gpio < 0)
161 return;
162
163 local_irq_save(flags);
164
165 c = gpio_desc[gpio].config;
166 c = (c & ~MFP_LPM_STATE_MASK) | lpm;
167 __mfp_config_gpio(gpio, c);
168
169 local_irq_restore(flags);
170 }
171
172 int gpio_set_wake(unsigned int gpio, unsigned int on)
173 {
174 struct gpio_desc *d;
175 unsigned long c, mux_taken;
176
177 if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
178 return -EINVAL;
179
180 d = &gpio_desc[gpio];
181 c = d->config;
182
183 if (!d->valid)
184 return -EINVAL;
185
186 /* Allow keypad GPIOs to wakeup system when
187 * configured as generic GPIOs.
188 */
189 if (d->keypad_gpio && (MFP_AF(d->config) == 0) &&
190 (d->config & MFP_LPM_CAN_WAKEUP)) {
191 if (on)
192 PKWR |= d->mask;
193 else
194 PKWR &= ~d->mask;
195 return 0;
196 }
197
198 mux_taken = (PWER & d->mux_mask) & (~d->mask);
199 if (on && mux_taken)
200 return -EBUSY;
201
202 if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
203 if (on) {
204 PWER = (PWER & ~d->mux_mask) | d->mask;
205
206 if (c & MFP_LPM_EDGE_RISE)
207 PRER |= d->mask;
208 else
209 PRER &= ~d->mask;
210
211 if (c & MFP_LPM_EDGE_FALL)
212 PFER |= d->mask;
213 else
214 PFER &= ~d->mask;
215 } else {
216 PWER &= ~d->mask;
217 PRER &= ~d->mask;
218 PFER &= ~d->mask;
219 }
220 }
221 return 0;
222 }
223
224 #ifdef CONFIG_PXA25x
225 static void __init pxa25x_mfp_init(void)
226 {
227 int i;
228
229 /* running before pxa_gpio_probe() */
230 #ifdef CONFIG_CPU_PXA26x
231 pxa_last_gpio = 89;
232 #else
233 pxa_last_gpio = 84;
234 #endif
235 for (i = 0; i <= pxa_last_gpio; i++)
236 gpio_desc[i].valid = 1;
237
238 for (i = 0; i <= 15; i++) {
239 gpio_desc[i].can_wakeup = 1;
240 gpio_desc[i].mask = GPIO_bit(i);
241 }
242
243 /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
244 * direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
245 */
246 for (i = 86; i <= pxa_last_gpio; i++)
247 gpio_desc[i].dir_inverted = 1;
248 }
249 #else
250 static inline void pxa25x_mfp_init(void) {}
251 #endif /* CONFIG_PXA25x */
252
253 #ifdef CONFIG_PXA27x
254 static int pxa27x_pkwr_gpio[] = {
255 13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
256 95, 96, 97, 98, 99, 100, 101, 102
257 };
258
259 int keypad_set_wake(unsigned int on)
260 {
261 unsigned int i, gpio, mask = 0;
262 struct gpio_desc *d;
263
264 for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
265
266 gpio = pxa27x_pkwr_gpio[i];
267 d = &gpio_desc[gpio];
268
269 /* skip if configured as generic GPIO */
270 if (MFP_AF(d->config) == 0)
271 continue;
272
273 if (d->config & MFP_LPM_CAN_WAKEUP)
274 mask |= gpio_desc[gpio].mask;
275 }
276
277 if (on)
278 PKWR |= mask;
279 else
280 PKWR &= ~mask;
281 return 0;
282 }
283
284 #define PWER_WEMUX2_GPIO38 (1 << 16)
285 #define PWER_WEMUX2_GPIO53 (2 << 16)
286 #define PWER_WEMUX2_GPIO40 (3 << 16)
287 #define PWER_WEMUX2_GPIO36 (4 << 16)
288 #define PWER_WEMUX2_MASK (7 << 16)
289 #define PWER_WEMUX3_GPIO31 (1 << 19)
290 #define PWER_WEMUX3_GPIO113 (2 << 19)
291 #define PWER_WEMUX3_MASK (3 << 19)
292
293 #define INIT_GPIO_DESC_MUXED(mux, gpio) \
294 do { \
295 gpio_desc[(gpio)].can_wakeup = 1; \
296 gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \
297 gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \
298 } while (0)
299
300 static void __init pxa27x_mfp_init(void)
301 {
302 int i, gpio;
303
304 pxa_last_gpio = 120; /* running before pxa_gpio_probe() */
305 for (i = 0; i <= pxa_last_gpio; i++) {
306 /* skip GPIO2, 5, 6, 7, 8, they are not
307 * valid pins allow configuration
308 */
309 if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8)
310 continue;
311
312 gpio_desc[i].valid = 1;
313 }
314
315 /* Keypad GPIOs */
316 for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
317 gpio = pxa27x_pkwr_gpio[i];
318 gpio_desc[gpio].can_wakeup = 1;
319 gpio_desc[gpio].keypad_gpio = 1;
320 gpio_desc[gpio].mask = 1 << i;
321 }
322
323 /* Overwrite GPIO13 as a PWER wakeup source */
324 for (i = 0; i <= 15; i++) {
325 /* skip GPIO2, 5, 6, 7, 8 */
326 if (GPIO_bit(i) & 0x1e4)
327 continue;
328
329 gpio_desc[i].can_wakeup = 1;
330 gpio_desc[i].mask = GPIO_bit(i);
331 }
332
333 gpio_desc[35].can_wakeup = 1;
334 gpio_desc[35].mask = PWER_WE35;
335
336 INIT_GPIO_DESC_MUXED(WEMUX3, 31);
337 INIT_GPIO_DESC_MUXED(WEMUX3, 113);
338 INIT_GPIO_DESC_MUXED(WEMUX2, 38);
339 INIT_GPIO_DESC_MUXED(WEMUX2, 53);
340 INIT_GPIO_DESC_MUXED(WEMUX2, 40);
341 INIT_GPIO_DESC_MUXED(WEMUX2, 36);
342 }
343 #else
344 static inline void pxa27x_mfp_init(void) {}
345 #endif /* CONFIG_PXA27x */
346
347 #ifdef CONFIG_PM
348 static unsigned long saved_gafr[2][4];
349 static unsigned long saved_gpdr[4];
350 static unsigned long saved_pgsr[4];
351
352 static int pxa2xx_mfp_suspend(void)
353 {
354 int i;
355
356 /* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */
357 for (i = 0; i < pxa_last_gpio; i++) {
358 if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
359 (GPDR(i) & GPIO_bit(i))) {
360 if (GPLR(i) & GPIO_bit(i))
361 PGSR(gpio_to_bank(i)) |= GPIO_bit(i);
362 else
363 PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
364 }
365 }
366
367 for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
368
369 saved_gafr[0][i] = GAFR_L(i);
370 saved_gafr[1][i] = GAFR_U(i);
371 saved_gpdr[i] = GPDR(i * 32);
372 saved_pgsr[i] = PGSR(i);
373
374 GPDR(i * 32) = gpdr_lpm[i];
375 }
376 return 0;
377 }
378
379 static void pxa2xx_mfp_resume(void)
380 {
381 int i;
382
383 for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
384 GAFR_L(i) = saved_gafr[0][i];
385 GAFR_U(i) = saved_gafr[1][i];
386 GPDR(i * 32) = saved_gpdr[i];
387 PGSR(i) = saved_pgsr[i];
388 }
389 PSSR = PSSR_RDH | PSSR_PH;
390 }
391 #else
392 #define pxa2xx_mfp_suspend NULL
393 #define pxa2xx_mfp_resume NULL
394 #endif
395
396 struct syscore_ops pxa2xx_mfp_syscore_ops = {
397 .suspend = pxa2xx_mfp_suspend,
398 .resume = pxa2xx_mfp_resume,
399 };
400
401 static int __init pxa2xx_mfp_init(void)
402 {
403 int i;
404
405 if (!cpu_is_pxa2xx())
406 return 0;
407
408 if (cpu_is_pxa25x())
409 pxa25x_mfp_init();
410
411 if (cpu_is_pxa27x())
412 pxa27x_mfp_init();
413
414 /* clear RDH bit to enable GPIO receivers after reset/sleep exit */
415 PSSR = PSSR_RDH;
416
417 /* initialize gafr_run[], pgsr_lpm[] from existing values */
418 for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
419 gpdr_lpm[i] = GPDR(i * 32);
420
421 return 0;
422 }
423 postcore_initcall(pxa2xx_mfp_init);