spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-realview / include / mach / irqs-pb11mp.h
blob34e255add21ec9b722a247fe369764f2d4b4d6f7
1 /*
2 * arch/arm/mach-realview/include/mach/irqs-pb11mp.h
4 * Copyright (C) 2008 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
21 #ifndef __MACH_IRQS_PB11MP_H
22 #define __MACH_IRQS_PB11MP_H
24 #define IRQ_TC11MP_GIC_START 32
25 #define IRQ_PB11MP_GIC_START 64
28 * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
30 #define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
31 #define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
32 #define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
33 #define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
34 #define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
35 #define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
36 #define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
37 #define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
38 #define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
39 #define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
40 #define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
41 #define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
42 #define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
43 #define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
44 #define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
45 #define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
47 #define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
48 #define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
49 #define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
50 #define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
51 #define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
52 #define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
53 #define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
54 #define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
55 #define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
56 #define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
57 #define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
58 #define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
60 #define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
61 #define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
62 #define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
65 * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
67 #define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
68 #define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
69 #define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
70 #define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
71 #define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
72 #define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
73 #define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
74 /* 9 reserved */
75 #define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
76 #define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
77 #define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
78 #define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
79 #define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
80 #define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
81 #define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
82 #define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
83 #define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
84 #define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
85 #define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
86 #define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
87 #define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
88 #define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
89 #define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
90 #define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
91 #define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
92 #define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
93 #define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
94 #define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
95 #define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
96 #define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
98 #define IRQ_PB11MP_SMC -1
99 #define IRQ_PB11MP_SCTL -1
101 #define NR_GIC_PB11MP 2
104 * Only define NR_IRQS if less than NR_IRQS_PB11MP
106 #define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96)
108 #if defined(CONFIG_MACH_REALVIEW_PB11MP)
110 #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
111 #undef NR_IRQS
112 #define NR_IRQS NR_IRQS_PB11MP
113 #endif
115 #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
116 #undef MAX_GIC_NR
117 #define MAX_GIC_NR NR_GIC_PB11MP
118 #endif
120 #endif /* CONFIG_MACH_REALVIEW_PB11MP */
122 #endif /* __MACH_IRQS_PB11MP_H */