spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-realview / include / mach / irqs-pbx.h
blob206a3001f46b4d23b3f01028eb5b731d06178c50
1 /*
2 * arch/arm/mach-realview/include/mach/irqs-pbx.h
4 * Copyright (C) 2009 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef __MACH_IRQS_PBX_H
21 #define __MACH_IRQS_PBX_H
23 #define IRQ_PBX_GIC_START 32
26 * PBX on-board gic irq sources
28 #define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */
29 #define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */
30 #define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */
31 #define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */
32 #define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */
33 #define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */
34 #define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */
35 #define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */
36 #define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */
37 /* 9 reserved */
38 #define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */
39 #define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */
40 #define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */
41 #define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */
42 #define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */
43 #define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */
44 #define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */
45 #define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */
46 #define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */
47 #define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */
48 #define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */
49 #define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */
50 #define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */
51 #define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */
52 #define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */
53 #define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */
54 #define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */
55 #define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */
56 #define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */
57 #define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */
58 #define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */
59 #define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */
61 #define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */
62 #define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33)
63 #define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34)
64 #define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35)
65 #define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36)
66 #define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37)
67 #define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38)
68 #define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39)
70 #define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */
71 #define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */
72 #define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */
73 /* ... */
74 #define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */
75 #define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 45)
76 #define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 46)
77 #define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 47)
79 /* ... */
80 #define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50)
81 #define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51)
82 #define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52)
83 #define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53)
85 #define IRQ_PBX_SMC -1
86 #define IRQ_PBX_SCTL -1
88 #define NR_GIC_PBX 1
91 * Only define NR_IRQS if less than NR_IRQS_PBX
93 #define NR_IRQS_PBX (IRQ_PBX_GIC_START + 96)
95 #if defined(CONFIG_MACH_REALVIEW_PBX)
97 #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBX)
98 #undef NR_IRQS
99 #define NR_IRQS NR_IRQS_PBX
100 #endif
102 #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBX)
103 #undef MAX_GIC_NR
104 #define MAX_GIC_NR NR_GIC_PBX
105 #endif
107 #endif /* CONFIG_MACH_REALVIEW_PBX */
109 #endif /* __MACH_IRQS_PBX_H */