arch/arm/mach-s5p64x0/clock-s5p6440.c

   1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
   2  *
   3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P6440 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/device.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/s5p64x0-clock.h>
  27
  28 #include <plat/cpu-freq.h>
  29 #include <plat/clock.h>
  30 #include <plat/cpu.h>
  31 #include <plat/pll.h>
  32 #include <plat/s5p-clock.h>
  33 #include <plat/clock-clksrc.h>
  34
  35 #include "common.h"
  36
  37 static u32 epll_div[][5] = {
  38         { 36000000,     0,      48, 1, 4 },
  39         { 48000000,     0,      32, 1, 3 },
  40         { 60000000,     0,      40, 1, 3 },
  41         { 72000000,     0,      48, 1, 3 },
  42         { 84000000,     0,      28, 1, 2 },
  43         { 96000000,     0,      32, 1, 2 },
  44         { 32768000,     45264,  43, 1, 4 },
  45         { 45158000,     6903,   30, 1, 3 },
  46         { 49152000,     50332,  32, 1, 3 },
  47         { 67738000,     10398,  45, 1, 3 },
  48         { 73728000,     9961,   49, 1, 3 }
  49 };
  50
  51 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
  52 {
  53         unsigned int epll_con, epll_con_k;
  54         unsigned int i;
  55
  56         if (clk->rate == rate)  /* Return if nothing changed */
  57                 return 0;
  58
  59         epll_con = __raw_readl(S5P64X0_EPLL_CON);
  60         epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
  61
  62         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  63         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  64
  65         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  66                  if (epll_div[i][0] == rate) {
  67                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  68                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  69                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  70                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  71                         break;
  72                 }
  73         }
  74
  75         if (i == ARRAY_SIZE(epll_div)) {
  76                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
  77                 return -EINVAL;
  78         }
  79
  80         __raw_writel(epll_con, S5P64X0_EPLL_CON);
  81         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
  82
  83         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
  84                         clk->rate, rate);
  85
  86         clk->rate = rate;
  87
  88         return 0;
  89 }
  90
  91 static struct clk_ops s5p6440_epll_ops = {
  92         .get_rate = s5p_epll_get_rate,
  93         .set_rate = s5p6440_epll_set_rate,
  94 };
  95
  96 static struct clksrc_clk clk_hclk = {
  97         .clk    = {
  98                 .name           = "clk_hclk",
  99                 .parent         = &clk_armclk.clk,
 100         },
 101         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
 102 };
 103
 104 static struct clksrc_clk clk_pclk = {
 105         .clk    = {
 106                 .name           = "clk_pclk",
 107                 .parent         = &clk_hclk.clk,
 108         },
 109         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 110 };
 111 static struct clksrc_clk clk_hclk_low = {
 112         .clk    = {
 113                 .name           = "clk_hclk_low",
 114         },
 115         .sources        = &clkset_hclk_low,
 116         .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
 117         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 118 };
 119
 120 static struct clksrc_clk clk_pclk_low = {
 121         .clk    = {
 122                 .name           = "clk_pclk_low",
 123                 .parent         = &clk_hclk_low.clk,
 124         },
 125         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 126 };
 127
 128 /*
 129  * The following clocks will be disabled during clock initialization. It is
 130  * recommended to keep the following clocks disabled until the driver requests
 131  * for enabling the clock.
 132  */
 133 static struct clk init_clocks_off[] = {
 134         {
 135                 .name           = "nand",
 136                 .parent         = &clk_hclk.clk,
 137                 .enable         = s5p64x0_mem_ctrl,
 138                 .ctrlbit        = (1 << 2),
 139         }, {
 140                 .name           = "post",
 141                 .parent         = &clk_hclk_low.clk,
 142                 .enable         = s5p64x0_hclk0_ctrl,
 143                 .ctrlbit        = (1 << 5)
 144         }, {
 145                 .name           = "2d",
 146                 .parent         = &clk_hclk.clk,
 147                 .enable         = s5p64x0_hclk0_ctrl,
 148                 .ctrlbit        = (1 << 8),
 149         }, {
 150                 .name           = "dma",
 151                 .devname        = "dma-pl330",
 152                 .parent         = &clk_hclk_low.clk,
 153                 .enable         = s5p64x0_hclk0_ctrl,
 154                 .ctrlbit        = (1 << 12),
 155         }, {
 156                 .name           = "hsmmc",
 157                 .devname        = "s3c-sdhci.0",
 158                 .parent         = &clk_hclk_low.clk,
 159                 .enable         = s5p64x0_hclk0_ctrl,
 160                 .ctrlbit        = (1 << 17),
 161         }, {
 162                 .name           = "hsmmc",
 163                 .devname        = "s3c-sdhci.1",
 164                 .parent         = &clk_hclk_low.clk,
 165                 .enable         = s5p64x0_hclk0_ctrl,
 166                 .ctrlbit        = (1 << 18),
 167         }, {
 168                 .name           = "hsmmc",
 169                 .devname        = "s3c-sdhci.2",
 170                 .parent         = &clk_hclk_low.clk,
 171                 .enable         = s5p64x0_hclk0_ctrl,
 172                 .ctrlbit        = (1 << 19),
 173         }, {
 174                 .name           = "otg",
 175                 .parent         = &clk_hclk_low.clk,
 176                 .enable         = s5p64x0_hclk0_ctrl,
 177                 .ctrlbit        = (1 << 20)
 178         }, {
 179                 .name           = "irom",
 180                 .parent         = &clk_hclk.clk,
 181                 .enable         = s5p64x0_hclk0_ctrl,
 182                 .ctrlbit        = (1 << 25),
 183         }, {
 184                 .name           = "lcd",
 185                 .parent         = &clk_hclk_low.clk,
 186                 .enable         = s5p64x0_hclk1_ctrl,
 187                 .ctrlbit        = (1 << 1),
 188         }, {
 189                 .name           = "hclk_fimgvg",
 190                 .parent         = &clk_hclk.clk,
 191                 .enable         = s5p64x0_hclk1_ctrl,
 192                 .ctrlbit        = (1 << 2),
 193         }, {
 194                 .name           = "tsi",
 195                 .parent         = &clk_hclk_low.clk,
 196                 .enable         = s5p64x0_hclk1_ctrl,
 197                 .ctrlbit        = (1 << 0),
 198         }, {
 199                 .name           = "watchdog",
 200                 .parent         = &clk_pclk_low.clk,
 201                 .enable         = s5p64x0_pclk_ctrl,
 202                 .ctrlbit        = (1 << 5),
 203         }, {
 204                 .name           = "rtc",
 205                 .parent         = &clk_pclk_low.clk,
 206                 .enable         = s5p64x0_pclk_ctrl,
 207                 .ctrlbit        = (1 << 6),
 208         }, {
 209                 .name           = "timers",
 210                 .parent         = &clk_pclk_low.clk,
 211                 .enable         = s5p64x0_pclk_ctrl,
 212                 .ctrlbit        = (1 << 7),
 213         }, {
 214                 .name           = "pcm",
 215                 .parent         = &clk_pclk_low.clk,
 216                 .enable         = s5p64x0_pclk_ctrl,
 217                 .ctrlbit        = (1 << 8),
 218         }, {
 219                 .name           = "adc",
 220                 .parent         = &clk_pclk_low.clk,
 221                 .enable         = s5p64x0_pclk_ctrl,
 222                 .ctrlbit        = (1 << 12),
 223         }, {
 224                 .name           = "i2c",
 225                 .parent         = &clk_pclk_low.clk,
 226                 .enable         = s5p64x0_pclk_ctrl,
 227                 .ctrlbit        = (1 << 17),
 228         }, {
 229                 .name           = "spi",
 230                 .devname        = "s3c64xx-spi.0",
 231                 .parent         = &clk_pclk_low.clk,
 232                 .enable         = s5p64x0_pclk_ctrl,
 233                 .ctrlbit        = (1 << 21),
 234         }, {
 235                 .name           = "spi",
 236                 .devname        = "s3c64xx-spi.1",
 237                 .parent         = &clk_pclk_low.clk,
 238                 .enable         = s5p64x0_pclk_ctrl,
 239                 .ctrlbit        = (1 << 22),
 240         }, {
 241                 .name           = "gps",
 242                 .parent         = &clk_pclk_low.clk,
 243                 .enable         = s5p64x0_pclk_ctrl,
 244                 .ctrlbit        = (1 << 25),
 245         }, {
 246                 .name           = "iis",
 247                 .devname        = "samsung-i2s.0",
 248                 .parent         = &clk_pclk_low.clk,
 249                 .enable         = s5p64x0_pclk_ctrl,
 250                 .ctrlbit        = (1 << 26),
 251         }, {
 252                 .name           = "dsim",
 253                 .parent         = &clk_pclk_low.clk,
 254                 .enable         = s5p64x0_pclk_ctrl,
 255                 .ctrlbit        = (1 << 28),
 256         }, {
 257                 .name           = "etm",
 258                 .parent         = &clk_pclk.clk,
 259                 .enable         = s5p64x0_pclk_ctrl,
 260                 .ctrlbit        = (1 << 29),
 261         }, {
 262                 .name           = "dmc0",
 263                 .parent         = &clk_pclk.clk,
 264                 .enable         = s5p64x0_pclk_ctrl,
 265                 .ctrlbit        = (1 << 30),
 266         }, {
 267                 .name           = "pclk_fimgvg",
 268                 .parent         = &clk_pclk.clk,
 269                 .enable         = s5p64x0_pclk_ctrl,
 270                 .ctrlbit        = (1 << 31),
 271         }, {
 272                 .name           = "mmc_48m",
 273                 .devname        = "s3c-sdhci.0",
 274                 .parent         = &clk_48m,
 275                 .enable         = s5p64x0_sclk_ctrl,
 276                 .ctrlbit        = (1 << 27),
 277         }, {
 278                 .name           = "mmc_48m",
 279                 .devname        = "s3c-sdhci.1",
 280                 .parent         = &clk_48m,
 281                 .enable         = s5p64x0_sclk_ctrl,
 282                 .ctrlbit        = (1 << 28),
 283         }, {
 284                 .name           = "mmc_48m",
 285                 .devname        = "s3c-sdhci.2",
 286                 .parent         = &clk_48m,
 287                 .enable         = s5p64x0_sclk_ctrl,
 288                 .ctrlbit        = (1 << 29),
 289         },
 290 };
 291
 292 /*
 293  * The following clocks will be enabled during clock initialization.
 294  */
 295 static struct clk init_clocks[] = {
 296         {
 297                 .name           = "intc",
 298                 .parent         = &clk_hclk.clk,
 299                 .enable         = s5p64x0_hclk0_ctrl,
 300                 .ctrlbit        = (1 << 1),
 301         }, {
 302                 .name           = "mem",
 303                 .parent         = &clk_hclk.clk,
 304                 .enable         = s5p64x0_hclk0_ctrl,
 305                 .ctrlbit        = (1 << 21),
 306         }, {
 307                 .name           = "uart",
 308                 .devname        = "s3c6400-uart.0",
 309                 .parent         = &clk_pclk_low.clk,
 310                 .enable         = s5p64x0_pclk_ctrl,
 311                 .ctrlbit        = (1 << 1),
 312         }, {
 313                 .name           = "uart",
 314                 .devname        = "s3c6400-uart.1",
 315                 .parent         = &clk_pclk_low.clk,
 316                 .enable         = s5p64x0_pclk_ctrl,
 317                 .ctrlbit        = (1 << 2),
 318         }, {
 319                 .name           = "uart",
 320                 .devname        = "s3c6400-uart.2",
 321                 .parent         = &clk_pclk_low.clk,
 322                 .enable         = s5p64x0_pclk_ctrl,
 323                 .ctrlbit        = (1 << 3),
 324         }, {
 325                 .name           = "uart",
 326                 .devname        = "s3c6400-uart.3",
 327                 .parent         = &clk_pclk_low.clk,
 328                 .enable         = s5p64x0_pclk_ctrl,
 329                 .ctrlbit        = (1 << 4),
 330         }, {
 331                 .name           = "gpio",
 332                 .parent         = &clk_pclk_low.clk,
 333                 .enable         = s5p64x0_pclk_ctrl,
 334                 .ctrlbit        = (1 << 18),
 335         },
 336 };
 337
 338 static struct clk clk_iis_cd_v40 = {
 339         .name           = "iis_cdclk_v40",
 340 };
 341
 342 static struct clk clk_pcm_cd = {
 343         .name           = "pcm_cdclk",
 344 };
 345
 346 static struct clk *clkset_group1_list[] = {
 347         &clk_mout_epll.clk,
 348         &clk_dout_mpll.clk,
 349         &clk_fin_epll,
 350 };
 351
 352 static struct clksrc_sources clkset_group1 = {
 353         .sources        = clkset_group1_list,
 354         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 355 };
 356
 357 static struct clk *clkset_uart_list[] = {
 358         &clk_mout_epll.clk,
 359         &clk_dout_mpll.clk,
 360 };
 361
 362 static struct clksrc_sources clkset_uart = {
 363         .sources        = clkset_uart_list,
 364         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 365 };
 366
 367 static struct clk *clkset_audio_list[] = {
 368         &clk_mout_epll.clk,
 369         &clk_dout_mpll.clk,
 370         &clk_fin_epll,
 371         &clk_iis_cd_v40,
 372         &clk_pcm_cd,
 373 };
 374
 375 static struct clksrc_sources clkset_audio = {
 376         .sources        = clkset_audio_list,
 377         .nr_sources     = ARRAY_SIZE(clkset_audio_list),
 378 };
 379
 380 static struct clksrc_clk clksrcs[] = {
 381         {
 382                 .clk    = {
 383                         .name           = "sclk_post",
 384                         .ctrlbit        = (1 << 10),
 385                         .enable         = s5p64x0_sclk_ctrl,
 386                 },
 387                 .sources = &clkset_group1,
 388                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 389                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 390         }, {
 391                 .clk    = {
 392                         .name           = "sclk_dispcon",
 393                         .ctrlbit        = (1 << 1),
 394                         .enable         = s5p64x0_sclk1_ctrl,
 395                 },
 396                 .sources = &clkset_group1,
 397                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 398                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 399         }, {
 400                 .clk    = {
 401                         .name           = "sclk_fimgvg",
 402                         .ctrlbit        = (1 << 2),
 403                         .enable         = s5p64x0_sclk1_ctrl,
 404                 },
 405                 .sources = &clkset_group1,
 406                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 407                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 408         }, {
 409                 .clk    = {
 410                         .name           = "sclk_audio2",
 411                         .ctrlbit        = (1 << 11),
 412                         .enable         = s5p64x0_sclk_ctrl,
 413                 },
 414                 .sources = &clkset_audio,
 415                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
 416                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
 417         },
 418 };
 419
 420 static struct clksrc_clk clk_sclk_mmc0 = {
 421         .clk    = {
 422                 .name           = "sclk_mmc",
 423                 .devname        = "s3c-sdhci.0",
 424                 .ctrlbit        = (1 << 24),
 425                 .enable         = s5p64x0_sclk_ctrl,
 426         },
 427         .sources = &clkset_group1,
 428         .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 429         .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 430 };
 431
 432 static struct clksrc_clk clk_sclk_mmc1 = {
 433         .clk    = {
 434                 .name           = "sclk_mmc",
 435                 .devname        = "s3c-sdhci.1",
 436                 .ctrlbit        = (1 << 25),
 437                 .enable         = s5p64x0_sclk_ctrl,
 438         },
 439         .sources = &clkset_group1,
 440         .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 441         .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 442 };
 443
 444 static struct clksrc_clk clk_sclk_mmc2 = {
 445         .clk    = {
 446                 .name           = "sclk_mmc",
 447                 .devname        = "s3c-sdhci.2",
 448                 .ctrlbit        = (1 << 26),
 449                 .enable         = s5p64x0_sclk_ctrl,
 450         },
 451         .sources = &clkset_group1,
 452         .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 453         .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 454 };
 455
 456 static struct clksrc_clk clk_sclk_uclk = {
 457         .clk    = {
 458                 .name           = "uclk1",
 459                 .ctrlbit        = (1 << 5),
 460                 .enable         = s5p64x0_sclk_ctrl,
 461         },
 462         .sources = &clkset_uart,
 463         .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 464         .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 465 };
 466
 467 static struct clksrc_clk clk_sclk_spi0 = {
 468         .clk    = {
 469                 .name           = "sclk_spi",
 470                 .devname        = "s3c64xx-spi.0",
 471                 .ctrlbit        = (1 << 20),
 472                 .enable         = s5p64x0_sclk_ctrl,
 473         },
 474         .sources = &clkset_group1,
 475         .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 476         .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 477 };
 478
 479 static struct clksrc_clk clk_sclk_spi1 = {
 480         .clk    = {
 481                 .name           = "sclk_spi",
 482                 .devname        = "s3c64xx-spi.1",
 483                 .ctrlbit        = (1 << 21),
 484                 .enable         = s5p64x0_sclk_ctrl,
 485         },
 486         .sources = &clkset_group1,
 487         .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 488         .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 489 };
 490
 491 /* Clock initialization code */
 492 static struct clksrc_clk *sysclks[] = {
 493         &clk_mout_apll,
 494         &clk_mout_epll,
 495         &clk_mout_mpll,
 496         &clk_dout_mpll,
 497         &clk_armclk,
 498         &clk_hclk,
 499         &clk_pclk,
 500         &clk_hclk_low,
 501         &clk_pclk_low,
 502 };
 503
 504 static struct clk dummy_apb_pclk = {
 505         .name           = "apb_pclk",
 506         .id             = -1,
 507 };
 508
 509 static struct clksrc_clk *clksrc_cdev[] = {
 510         &clk_sclk_uclk,
 511         &clk_sclk_spi0,
 512         &clk_sclk_spi1,
 513         &clk_sclk_mmc0,
 514         &clk_sclk_mmc1,
 515         &clk_sclk_mmc2
 516 };
 517
 518 static struct clk_lookup s5p6440_clk_lookup[] = {
 519         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
 520         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 521         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
 522         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
 523         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 524         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
 525         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 526         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 527 };
 528
 529 void __init_or_cpufreq s5p6440_setup_clocks(void)
 530 {
 531         struct clk *xtal_clk;
 532
 533         unsigned long xtal;
 534         unsigned long fclk;
 535         unsigned long hclk;
 536         unsigned long hclk_low;
 537         unsigned long pclk;
 538         unsigned long pclk_low;
 539
 540         unsigned long apll;
 541         unsigned long mpll;
 542         unsigned long epll;
 543         unsigned int ptr;
 544
 545         /* Set S5P6440 functions for clk_fout_epll */
 546
 547         clk_fout_epll.enable = s5p_epll_enable;
 548         clk_fout_epll.ops = &s5p6440_epll_ops;
 549
 550         clk_48m.enable = s5p64x0_clk48m_ctrl;
 551
 552         xtal_clk = clk_get(NULL, "ext_xtal");
 553         BUG_ON(IS_ERR(xtal_clk));
 554
 555         xtal = clk_get_rate(xtal_clk);
 556         clk_put(xtal_clk);
 557
 558         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 559         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 560         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 561                                 __raw_readl(S5P64X0_EPLL_CON_K));
 562
 563         clk_fout_apll.rate = apll;
 564         clk_fout_mpll.rate = mpll;
 565         clk_fout_epll.rate = epll;
 566
 567         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 568                         " E=%ld.%ldMHz\n",
 569                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 570
 571         fclk = clk_get_rate(&clk_armclk.clk);
 572         hclk = clk_get_rate(&clk_hclk.clk);
 573         pclk = clk_get_rate(&clk_pclk.clk);
 574         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 575         pclk_low = clk_get_rate(&clk_pclk_low.clk);
 576
 577         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 578                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 579                         print_mhz(hclk), print_mhz(hclk_low),
 580                         print_mhz(pclk), print_mhz(pclk_low));
 581
 582         clk_f.rate = fclk;
 583         clk_h.rate = hclk;
 584         clk_p.rate = pclk;
 585
 586         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 587                 s3c_set_clksrc(&clksrcs[ptr], true);
 588 }
 589
 590 static struct clk *clks[] __initdata = {
 591         &clk_ext,
 592         &clk_iis_cd_v40,
 593         &clk_pcm_cd,
 594 };
 595
 596 void __init s5p6440_register_clocks(void)
 597 {
 598         int ptr;
 599
 600         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 601
 602         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 603                 s3c_register_clksrc(sysclks[ptr], 1);
 604
 605         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 606         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 607         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
 608                 s3c_register_clksrc(clksrc_cdev[ptr], 1);
 609
 610         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 611         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 612         clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
 613
 614         s3c24xx_register_clock(&dummy_apb_pclk);
 615
 616         s3c_pwmclk_init();
 617 }