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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-shmobile / intc-r8a7740.c
blob272c84c20c839d5415bc9953c7b234a4f053e676
1 /*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/io.h>
26 #include <linux/sh_intc.h>
27 #include <mach/intc.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30
31 /*
32 * INTCA
33 */
34 enum {
35 UNUSED_INTCA = 0,
36
37 /* interrupt sources INTCA */
38 DIRC,
39 ATAPI,
40 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
41 AP_ARM_COMMTX, AP_ARM_COMMRX,
42 MFI, MFIS,
43 BBIF1, BBIF2,
44 USBHSDMAC,
45 USBF_OUL_SOF, USBF_IXL_INT,
46 SGX540,
47 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
48 CMT2,
49 CMT3,
50 KEYSC,
51 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
52 MSIOF2, MSIOF1,
53 SCIFA4, SCIFA5, SCIFB,
54 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
55 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
56 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
57 AP_ARM_L2CINT,
58 IRDA,
59 TPU0,
60 SCIFA6, SCIFA7,
61 GbEther,
62 ICBS0,
63 DDM,
64 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
65 RWDT0,
66 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
67 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
73 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
74 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
75 SPU2_0, SPU2_1,
76 FSI, FMSI,
77 IPMMU,
78 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
79 MFIS2,
80 CPORTR2S,
81 CMT14, CMT15,
82 MMCIF_0, MMCIF_1, MMCIF_2,
83 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
84 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
85
86 /* interrupt groups INTCA */
87 DMAC1_1, DMAC1_2,
88 DMAC2_1, DMAC2_2,
89 DMAC3_1, DMAC3_2,
90 AP_ARM1, AP_ARM2,
91 SDHI0, SDHI1, SDHI2,
92 SHWYSTAT,
93 USBF, USBH1, USBH2,
94 RSPI, SPU2, FLCTL, IIC1,
95 };
96
97 static struct intc_vect intca_vectors[] __initdata = {
98 INTC_VECT(DIRC, 0x0560),
99 INTC_VECT(ATAPI, 0x05E0),
100 INTC_VECT(IIC1_ALI, 0x0780),
101 INTC_VECT(IIC1_TACKI, 0x07A0),
102 INTC_VECT(IIC1_WAITI, 0x07C0),
103 INTC_VECT(IIC1_DTEI, 0x07E0),
104 INTC_VECT(AP_ARM_COMMTX, 0x0840),
105 INTC_VECT(AP_ARM_COMMRX, 0x0860),
106 INTC_VECT(MFI, 0x0900),
107 INTC_VECT(MFIS, 0x0920),
108 INTC_VECT(BBIF1, 0x0940),
109 INTC_VECT(BBIF2, 0x0960),
110 INTC_VECT(USBHSDMAC, 0x0A00),
111 INTC_VECT(USBF_OUL_SOF, 0x0A20),
112 INTC_VECT(USBF_IXL_INT, 0x0A40),
113 INTC_VECT(SGX540, 0x0A60),
114 INTC_VECT(CMT1_0, 0x0B00),
115 INTC_VECT(CMT1_1, 0x0B20),
116 INTC_VECT(CMT1_2, 0x0B40),
117 INTC_VECT(CMT1_3, 0x0B60),
118 INTC_VECT(CMT2, 0x0B80),
119 INTC_VECT(CMT3, 0x0BA0),
120 INTC_VECT(KEYSC, 0x0BE0),
121 INTC_VECT(SCIFA0, 0x0C00),
122 INTC_VECT(SCIFA1, 0x0C20),
123 INTC_VECT(SCIFA2, 0x0C40),
124 INTC_VECT(SCIFA3, 0x0C60),
125 INTC_VECT(MSIOF2, 0x0C80),
126 INTC_VECT(MSIOF1, 0x0D00),
127 INTC_VECT(SCIFA4, 0x0D20),
128 INTC_VECT(SCIFA5, 0x0D40),
129 INTC_VECT(SCIFB, 0x0D60),
130 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
131 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
132 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
133 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
134 INTC_VECT(SDHI0_0, 0x0E00),
135 INTC_VECT(SDHI0_1, 0x0E20),
136 INTC_VECT(SDHI0_2, 0x0E40),
137 INTC_VECT(SDHI0_3, 0x0E60),
138 INTC_VECT(SDHI1_0, 0x0E80),
139 INTC_VECT(SDHI1_1, 0x0EA0),
140 INTC_VECT(SDHI1_2, 0x0EC0),
141 INTC_VECT(SDHI1_3, 0x0EE0),
142 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
143 INTC_VECT(IRDA, 0x0480),
144 INTC_VECT(TPU0, 0x04A0),
145 INTC_VECT(SCIFA6, 0x04C0),
146 INTC_VECT(SCIFA7, 0x04E0),
147 INTC_VECT(GbEther, 0x0500),
148 INTC_VECT(ICBS0, 0x0540),
149 INTC_VECT(DDM, 0x1140),
150 INTC_VECT(SDHI2_0, 0x1200),
151 INTC_VECT(SDHI2_1, 0x1220),
152 INTC_VECT(SDHI2_2, 0x1240),
153 INTC_VECT(SDHI2_3, 0x1260),
154 INTC_VECT(RWDT0, 0x1280),
155 INTC_VECT(DMAC1_1_DEI0, 0x2000),
156 INTC_VECT(DMAC1_1_DEI1, 0x2020),
157 INTC_VECT(DMAC1_1_DEI2, 0x2040),
158 INTC_VECT(DMAC1_1_DEI3, 0x2060),
159 INTC_VECT(DMAC1_2_DEI4, 0x2080),
160 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
161 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
162 INTC_VECT(DMAC2_1_DEI0, 0x2100),
163 INTC_VECT(DMAC2_1_DEI1, 0x2120),
164 INTC_VECT(DMAC2_1_DEI2, 0x2140),
165 INTC_VECT(DMAC2_1_DEI3, 0x2160),
166 INTC_VECT(DMAC2_2_DEI4, 0x2180),
167 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
168 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
169 INTC_VECT(DMAC3_1_DEI0, 0x2200),
170 INTC_VECT(DMAC3_1_DEI1, 0x2220),
171 INTC_VECT(DMAC3_1_DEI2, 0x2240),
172 INTC_VECT(DMAC3_1_DEI3, 0x2260),
173 INTC_VECT(DMAC3_2_DEI4, 0x2280),
174 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
175 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
176 INTC_VECT(SHWYSTAT_RT, 0x1300),
177 INTC_VECT(SHWYSTAT_HS, 0x1320),
178 INTC_VECT(SHWYSTAT_COM, 0x1340),
179 INTC_VECT(USBH_INT, 0x1540),
180 INTC_VECT(USBH_OHCI, 0x1560),
181 INTC_VECT(USBH_EHCI, 0x1580),
182 INTC_VECT(USBH_PME, 0x15A0),
183 INTC_VECT(USBH_BIND, 0x15C0),
184 INTC_VECT(RSPI_OVRF, 0x1780),
185 INTC_VECT(RSPI_SPTEF, 0x17A0),
186 INTC_VECT(RSPI_SPRF, 0x17C0),
187 INTC_VECT(SPU2_0, 0x1800),
188 INTC_VECT(SPU2_1, 0x1820),
189 INTC_VECT(FSI, 0x1840),
190 INTC_VECT(FMSI, 0x1860),
191 INTC_VECT(IPMMU, 0x1920),
192 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
193 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
194 INTC_VECT(MFIS2, 0x1A00),
195 INTC_VECT(CPORTR2S, 0x1A20),
196 INTC_VECT(CMT14, 0x1A40),
197 INTC_VECT(CMT15, 0x1A60),
198 INTC_VECT(MMCIF_0, 0x1AA0),
199 INTC_VECT(MMCIF_1, 0x1AC0),
200 INTC_VECT(MMCIF_2, 0x1AE0),
201 INTC_VECT(SIM_ERI, 0x1C00),
202 INTC_VECT(SIM_RXI, 0x1C20),
203 INTC_VECT(SIM_TXI, 0x1C40),
204 INTC_VECT(SIM_TEI, 0x1C60),
205 INTC_VECT(STPRO_0, 0x1C80),
206 INTC_VECT(STPRO_1, 0x1CA0),
207 INTC_VECT(STPRO_2, 0x1CC0),
208 INTC_VECT(STPRO_3, 0x1CE0),
209 INTC_VECT(STPRO_4, 0x1D00),
210 };
211
212 static struct intc_group intca_groups[] __initdata = {
213 INTC_GROUP(DMAC1_1,
214 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
215 INTC_GROUP(DMAC1_2,
216 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
217 INTC_GROUP(DMAC2_1,
218 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
219 INTC_GROUP(DMAC2_2,
220 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
221 INTC_GROUP(DMAC3_1,
222 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
223 INTC_GROUP(DMAC3_2,
224 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
225 INTC_GROUP(AP_ARM1,
226 AP_ARM_COMMTX, AP_ARM_COMMRX),
227 INTC_GROUP(AP_ARM2,
228 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
229 INTC_GROUP(USBF,
230 USBF_OUL_SOF, USBF_IXL_INT),
231 INTC_GROUP(SDHI0,
232 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
233 INTC_GROUP(SDHI1,
234 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
235 INTC_GROUP(SDHI2,
236 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
237 INTC_GROUP(SHWYSTAT,
238 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
239 INTC_GROUP(USBH1, /* FIXME */
240 USBH_INT, USBH_OHCI),
241 INTC_GROUP(USBH2, /* FIXME */
242 USBH_EHCI,
243 USBH_PME, USBH_BIND),
244 INTC_GROUP(RSPI,
245 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
246 INTC_GROUP(SPU2,
247 SPU2_0, SPU2_1),
248 INTC_GROUP(FLCTL,
249 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
250 INTC_GROUP(IIC1,
251 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
252 };
253
254 static struct intc_mask_reg intca_mask_registers[] __initdata = {
255 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
256 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
257 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
258 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
259 { ATAPI, 0, DIRC, 0,
260 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
261 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
262 { 0, 0, 0, 0,
263 BBIF1, BBIF2, MFIS, MFI } },
264 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
265 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
266 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
267 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
268 { DDM, 0, 0, 0,
269 0, 0, 0, 0 } },
270 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
271 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
272 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
273 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
274 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
275 0, 0, MSIOF2, 0 } },
276 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
277 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
278 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
279 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
280 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
281 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
282 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
283 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
284 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
285 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
286 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
287 0, 0, 0, 0 } },
288 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
289 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
290 ICBS0, 0, 0, 0 } },
291 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
292 { 0, 0, TPU0, SCIFA6,
293 SCIFA7, GbEther, 0, 0 } },
294 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
295 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
296 0, CMT3, 0, RWDT0 } },
297 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
298 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
299 0, 0, 0, 0 } },
300 /* IMR1A3 / IMCR1A3 */
301 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
302 { 0, 0, USBH_INT, USBH_OHCI,
303 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
304 /* IMR3A3 / IMCR3A3 */
305 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
306 { 0, 0, 0, 0,
307 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
308 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
309 { SPU2_0, SPU2_1, FSI, FMSI,
310 0, 0, 0, 0 } },
311 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
312 { 0, IPMMU, 0, 0,
313 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
314 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
315 { MFIS2, CPORTR2S, CMT14, CMT15,
316 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
317 /* IMR8A3 / IMCR8A3 */
318 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
319 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
320 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
321 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
322 { STPRO_4, 0, 0, 0,
323 0, 0, 0, 0 } },
324 };
325
326 static struct intc_prio_reg intca_prio_registers[] __initdata = {
327 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
328 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
329 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
330 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
331 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
332 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
333 SGX540, CMT1_0 } },
334 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
335 SCIFA2, SCIFA3 } },
336 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
337 FLCTL, SDHI0 } },
338 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
339 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
340 AP_ARM_L2CINT, 0 } },
341 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
342 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
343 SCIFA7, GbEther } },
344 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
345 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
346 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
347 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
348 /* IPRBA3 */
349 /* IPRCA3 */
350 /* IPRDA3 */
351 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
352 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
353 /* IPRGA3 */
354 /* IPRHA3 */
355 /* IPRIA3 */
356 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
357 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
358 /* IPRLA3 */
359 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
360 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
361 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
362 CMT14, CMT15 } },
363 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
364 /* IPRQA3 */
365 /* IPRRA3 */
366 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
367 SIM_TXI, SIM_TEI } },
368 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
369 STPRO_2, STPRO_3 } },
370 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
371 };
372
373 static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
374 intca_vectors, intca_groups,
375 intca_mask_registers, intca_prio_registers,
376 NULL);
377
378 INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
379 INTC_VECT, "r8a7740-intca-irq-pins");
380
381
382 /*
383 * INTCS
384 */
385 enum {
386 UNUSED_INTCS = 0,
387
388 INTCS,
389
390 /* interrupt sources INTCS */
391
392 /* HUDI */
393 /* STPRO */
394 /* RTDMAC(1) */
395 VPU5HA2,
396 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
397 /* MFI */
398 /* BBIF2 */
399 VPU5F,
400 _2DG_BRK_INT,
401 /* SGX540 */
402 /* 2DDMAC */
403 /* IPMMU */
404 /* RTDMAC 2 */
405 /* KEYSC */
406 /* MSIOF */
407 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
408 TMU0_0, TMU0_1, TMU0_2,
409 CMT0,
410 /* CMT2 */
411 LMB,
412 CTI,
413 VOU,
414 /* RWDT0 */
415 ICB,
416 VIO6C,
417 CEU20, CEU21,
418 JPU,
419 LCDC0,
420 LCRC,
421 /* RTDMAC2(1) */
422 /* RTDMAC2(2) */
423 LCDC1,
424 /* SPU2 */
425 /* FSI */
426 /* FMSI */
427 TMU1_0, TMU1_1, TMU1_2,
428 CMT4,
429 DISP,
430 DSRV,
431 /* MFIS2 */
432 CPORTS2R,
433
434 /* interrupt groups INTCS */
435 _2DG1,
436 IIC0, TMU1,
437 };
438
439 static struct intc_vect intcs_vectors[] = {
440 /* HUDI */
441 /* STPRO */
442 /* RTDMAC(1) */
443 INTCS_VECT(VPU5HA2, 0x0880),
444 INTCS_VECT(_2DG_TRAP, 0x08A0),
445 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
446 INTCS_VECT(_2DG_CER_INT, 0x08E0),
447 /* MFI */
448 /* BBIF2 */
449 INTCS_VECT(VPU5F, 0x0980),
450 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
451 /* SGX540 */
452 /* 2DDMAC */
453 /* IPMMU */
454 /* RTDMAC(2) */
455 /* KEYSC */
456 /* MSIOF */
457 INTCS_VECT(IIC0_ALI, 0x0E00),
458 INTCS_VECT(IIC0_TACKI, 0x0E20),
459 INTCS_VECT(IIC0_WAITI, 0x0E40),
460 INTCS_VECT(IIC0_DTEI, 0x0E60),
461 INTCS_VECT(TMU0_0, 0x0E80),
462 INTCS_VECT(TMU0_1, 0x0EA0),
463 INTCS_VECT(TMU0_2, 0x0EC0),
464 INTCS_VECT(CMT0, 0x0F00),
465 /* CMT2 */
466 INTCS_VECT(LMB, 0x0F60),
467 INTCS_VECT(CTI, 0x0400),
468 INTCS_VECT(VOU, 0x0420),
469 /* RWDT0 */
470 INTCS_VECT(ICB, 0x0480),
471 INTCS_VECT(VIO6C, 0x04E0),
472 INTCS_VECT(CEU20, 0x0500),
473 INTCS_VECT(CEU21, 0x0520),
474 INTCS_VECT(JPU, 0x0560),
475 INTCS_VECT(LCDC0, 0x0580),
476 INTCS_VECT(LCRC, 0x05A0),
477 /* RTDMAC2(1) */
478 /* RTDMAC2(2) */
479 INTCS_VECT(LCDC1, 0x1780),
480 /* SPU2 */
481 /* FSI */
482 /* FMSI */
483 INTCS_VECT(TMU1_0, 0x1900),
484 INTCS_VECT(TMU1_1, 0x1920),
485 INTCS_VECT(TMU1_2, 0x1940),
486 INTCS_VECT(CMT4, 0x1980),
487 INTCS_VECT(DISP, 0x19A0),
488 INTCS_VECT(DSRV, 0x19C0),
489 /* MFIS2 */
490 INTCS_VECT(CPORTS2R, 0x1A20),
491
492 INTC_VECT(INTCS, 0xf80),
493 };
494
495 static struct intc_group intcs_groups[] __initdata = {
496 INTC_GROUP(_2DG1, /*FIXME*/
497 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
498 INTC_GROUP(IIC0,
499 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
500 INTC_GROUP(TMU1,
501 TMU1_0, TMU1_1, TMU1_2),
502 };
503
504 static struct intc_mask_reg intcs_mask_registers[] = {
505 /* IMR0SA / IMCR0SA */ /* all 0 */
506 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
507 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
508 0, 0, 0, 0 /*STPRO*/ } },
509 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
510 { 0/*STPRO*/, 0, CEU21, VPU5F,
511 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
512 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
513 { 0, 0, 0, 0, /*2DDMAC*/
514 VIO6C, 0, 0, ICB } },
515 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
516 { 0, 0, VOU, CTI,
517 JPU, 0, LCRC, LCDC0 } },
518 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
519 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
520 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
521 { 0, TMU0_2, TMU0_1, TMU0_0,
522 0, 0, 0, 0 } },
523 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
524 { 0, 0, 0, 0,
525 CEU20, 0, 0, 0 } },
526 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
527 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
528 0, 0, 0, 0 } },
529 /* IMR10SA / IMCR10SA */ /*IPMMU*/
530 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
531 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
532 0, _2DG_BRK_INT, LMB, 0 } },
533 /* IMR12SA / IMCR12SA */
534 /* IMR13SA / IMCR13SA */
535 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
536 /* IMR1SA3 / IMCR1SA3 */
537 /* IMR2SA3 / IMCR2SA3 */
538 /* IMR3SA3 / IMCR3SA3 */
539 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
540 { 0, 0, 0, 0,
541 LCDC1, 0, 0, 0 } },
542 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
543 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
544 { TMU1_0, TMU1_1, TMU1_2, 0,
545 CMT4, DISP, DSRV, 0 } },
546 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
547 { 0/*MFIS2*/, CPORTS2R, 0, 0,
548 0, 0, 0, 0 } },
549 { /* INTAMASK */ 0xffd20104, 0, 16,
550 { 0, 0, 0, 0, 0, 0, 0, 0,
551 0, 0, 0, 0, 0, 0, 0, INTCS } },
552 };
553
554 /* Priority is needed for INTCA to receive the INTCS interrupt */
555 static struct intc_prio_reg intcs_prio_registers[] = {
556 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
557 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
558 /* IPRCS */ /*BBIF2*/
559 /* IPRDS */
560 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
561 0/*MFI*/, VPU5F } },
562 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
563 0/*CMT2*/, CMT0 } },
564 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
565 TMU0_2, _2DG1 } },
566 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
567 _2DG_BRK_INT/*FIXME*/ } },
568 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
569 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
570 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
571 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
572 /* IPRMS */ /*RWDT0*/
573 /* IPRAS3 */ /*RTDMAC2(1)*/
574 /* IPRBS3 */ /*RTDMAC2(2)*/
575 /* IPRCS3 */
576 /* IPRDS3 */
577 /* IPRES3 */
578 /* IPRFS3 */
579 /* IPRGS3 */
580 /* IPRHS3 */
581 /* IPRIS3 */
582 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
583 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
584 /* IPRLS3 */
585 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
586 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
587 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
588 /* IPRPS3 */
589 };
590
591 static struct resource intcs_resources[] __initdata = {
592 [0] = {
593 .start = 0xffd20000,
594 .end = 0xffd201ff,
595 .flags = IORESOURCE_MEM,
596 },
597 [1] = {
598 .start = 0xffd50000,
599 .end = 0xffd501ff,
600 .flags = IORESOURCE_MEM,
601 }
602 };
603
604 static struct intc_desc intcs_desc __initdata = {
605 .name = "r8a7740-intcs",
606 .resource = intcs_resources,
607 .num_resources = ARRAY_SIZE(intcs_resources),
608 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
609 intcs_prio_registers, NULL, NULL),
610 };
611
612 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
613 {
614 void __iomem *reg = (void *)irq_get_handler_data(irq);
615 unsigned int evtcodeas = ioread32(reg);
616
617 generic_handle_irq(intcs_evt2irq(evtcodeas));
618 }
619
620 void __init r8a7740_init_irq(void)
621 {
622 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
623
624 register_intc_controller(&intca_desc);
625 register_intc_controller(&intca_irq_pins_desc);
626 register_intc_controller(&intcs_desc);
627
628 /* demux using INTEVTSA */
629 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
630 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
631 }