arch/arm/mach-shmobile/smp-sh73a0.c

   1 /*
   2  * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2010  Takashi Yoshii
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <mach/common.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/smp_twd.h>
  29 #include <asm/hardware/gic.h>
  30
  31 #define WUPCR           0xe6151010
  32 #define SRESCR          0xe6151018
  33 #define PSTR            0xe6151040
  34 #define SBAR            0xe6180020
  35 #define APARMBAREA      0xe6f10020
  36
  37 static void __iomem *scu_base_addr(void)
  38 {
  39         return (void __iomem *)0xf0000000;
  40 }
  41
  42 static DEFINE_SPINLOCK(scu_lock);
  43 static unsigned long tmp;
  44
  45 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
  46 {
  47         void __iomem *scu_base = scu_base_addr();
  48
  49         spin_lock(&scu_lock);
  50         tmp = __raw_readl(scu_base + 8);
  51         tmp &= ~clr;
  52         tmp |= set;
  53         spin_unlock(&scu_lock);
  54
  55         /* disable cache coherency after releasing the lock */
  56         __raw_writel(tmp, scu_base + 8);
  57 }
  58
  59 unsigned int __init sh73a0_get_core_count(void)
  60 {
  61         void __iomem *scu_base = scu_base_addr();
  62
  63 #ifdef CONFIG_HAVE_ARM_TWD
  64         /* twd_base needs to be initialized before percpu_timer_setup() */
  65         twd_base = (void __iomem *)0xf0000600;
  66 #endif
  67
  68         return scu_get_core_count(scu_base);
  69 }
  70
  71 void __cpuinit sh73a0_secondary_init(unsigned int cpu)
  72 {
  73         gic_secondary_init(0);
  74 }
  75
  76 int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
  77 {
  78         cpu = cpu_logical_map(cpu);
  79
  80         /* enable cache coherency */
  81         modify_scu_cpu_psr(0, 3 << (cpu * 8));
  82
  83         if (((__raw_readl(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
  84                 __raw_writel(1 << cpu, __io(WUPCR));    /* wake up */
  85         else
  86                 __raw_writel(1 << cpu, __io(SRESCR));   /* reset */
  87
  88         return 0;
  89 }
  90
  91 void __init sh73a0_smp_prepare_cpus(void)
  92 {
  93         int cpu = cpu_logical_map(0);
  94
  95         scu_enable(scu_base_addr());
  96
  97         /* Map the reset vector (in headsmp.S) */
  98         __raw_writel(0, __io(APARMBAREA));      /* 4k */
  99         __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
 100
 101         /* enable cache coherency on CPU0 */
 102         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 103 }