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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-tegra / tegra2_clocks.c
blobff9e6b6c046077012214778426a944a42db9806f
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
28
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34 #include "tegra2_emc.h"
35
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
40
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
45
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
48
49 #define OSC_CTRL 0x50
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
59
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
75 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
76
77 #define SDMMC_CLK_INT_FB_SEL (1 << 23)
78 #define SDMMC_CLK_INT_FB_DLY_SHIFT 16
79 #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
80
81 #define PLL_BASE 0x0
82 #define PLL_BASE_BYPASS (1<<31)
83 #define PLL_BASE_ENABLE (1<<30)
84 #define PLL_BASE_REF_ENABLE (1<<29)
85 #define PLL_BASE_OVERRIDE (1<<28)
86 #define PLL_BASE_DIVP_MASK (0x7<<20)
87 #define PLL_BASE_DIVP_SHIFT 20
88 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
89 #define PLL_BASE_DIVN_SHIFT 8
90 #define PLL_BASE_DIVM_MASK (0x1F)
91 #define PLL_BASE_DIVM_SHIFT 0
92
93 #define PLL_OUT_RATIO_MASK (0xFF<<8)
94 #define PLL_OUT_RATIO_SHIFT 8
95 #define PLL_OUT_OVERRIDE (1<<2)
96 #define PLL_OUT_CLKEN (1<<1)
97 #define PLL_OUT_RESET_DISABLE (1<<0)
98
99 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
100
101 #define PLL_MISC_DCCON_SHIFT 20
102 #define PLL_MISC_CPCON_SHIFT 8
103 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
104 #define PLL_MISC_LFCON_SHIFT 4
105 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
106 #define PLL_MISC_VCOCON_SHIFT 0
107 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
108
109 #define PLLU_BASE_POST_DIV (1<<20)
110
111 #define PLLD_MISC_CLKENABLE (1<<30)
112 #define PLLD_MISC_DIV_RST (1<<23)
113 #define PLLD_MISC_DCCON_SHIFT 12
114
115 #define PLLE_MISC_READY (1 << 15)
116
117 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
118 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
119 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
120
121 #define SUPER_CLK_MUX 0x00
122 #define SUPER_STATE_SHIFT 28
123 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
124 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
125 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
126 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
127 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
128 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
129 #define SUPER_SOURCE_MASK 0xF
130 #define SUPER_FIQ_SOURCE_SHIFT 12
131 #define SUPER_IRQ_SOURCE_SHIFT 8
132 #define SUPER_RUN_SOURCE_SHIFT 4
133 #define SUPER_IDLE_SOURCE_SHIFT 0
134
135 #define SUPER_CLK_DIVIDER 0x04
136
137 #define BUS_CLK_DISABLE (1<<3)
138 #define BUS_CLK_DIV_MASK 0x3
139
140 #define PMC_CTRL 0x0
141 #define PMC_CTRL_BLINK_ENB (1 << 7)
142
143 #define PMC_DPD_PADS_ORIDE 0x1c
144 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
145
146 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
147 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
148 #define PMC_BLINK_TIMER_ENB (1 << 15)
149 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
150 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
151
152 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
153 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
154
155 /*
156 * Some clocks share a register with other clocks. Any clock op that
157 * non-atomically modifies a register used by another clock must lock
158 * clock_register_lock first.
159 */
160 static DEFINE_SPINLOCK(clock_register_lock);
161
162 /*
163 * Some peripheral clocks share an enable bit, so refcount the enable bits
164 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
165 */
166 static int tegra_periph_clk_enable_refcount[3 * 32];
167
168 #define clk_writel(value, reg) \
169 __raw_writel(value, reg_clk_base + (reg))
170 #define clk_readl(reg) \
171 __raw_readl(reg_clk_base + (reg))
172 #define pmc_writel(value, reg) \
173 __raw_writel(value, reg_pmc_base + (reg))
174 #define pmc_readl(reg) \
175 __raw_readl(reg_pmc_base + (reg))
176
177 static unsigned long clk_measure_input_freq(void)
178 {
179 u32 clock_autodetect;
180 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
181 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
182 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
183 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
184 return 12000000;
185 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
186 return 13000000;
187 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
188 return 19200000;
189 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
190 return 26000000;
191 } else {
192 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
193 BUG();
194 return 0;
195 }
196 }
197
198 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
199 {
200 s64 divider_u71 = parent_rate * 2;
201 divider_u71 += rate - 1;
202 do_div(divider_u71, rate);
203
204 if (divider_u71 - 2 < 0)
205 return 0;
206
207 if (divider_u71 - 2 > 255)
208 return -EINVAL;
209
210 return divider_u71 - 2;
211 }
212
213 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
214 {
215 s64 divider_u16;
216
217 divider_u16 = parent_rate;
218 divider_u16 += rate - 1;
219 do_div(divider_u16, rate);
220
221 if (divider_u16 - 1 < 0)
222 return 0;
223
224 if (divider_u16 - 1 > 255)
225 return -EINVAL;
226
227 return divider_u16 - 1;
228 }
229
230 /* clk_m functions */
231 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
232 {
233 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
234
235 c->rate = clk_measure_input_freq();
236 switch (c->rate) {
237 case 12000000:
238 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
239 break;
240 case 13000000:
241 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
242 break;
243 case 19200000:
244 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
245 break;
246 case 26000000:
247 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
248 break;
249 default:
250 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
251 BUG();
252 }
253 clk_writel(auto_clock_control, OSC_CTRL);
254 return c->rate;
255 }
256
257 static void tegra2_clk_m_init(struct clk *c)
258 {
259 pr_debug("%s on clock %s\n", __func__, c->name);
260 tegra2_clk_m_autodetect_rate(c);
261 }
262
263 static int tegra2_clk_m_enable(struct clk *c)
264 {
265 pr_debug("%s on clock %s\n", __func__, c->name);
266 return 0;
267 }
268
269 static void tegra2_clk_m_disable(struct clk *c)
270 {
271 pr_debug("%s on clock %s\n", __func__, c->name);
272 BUG();
273 }
274
275 static struct clk_ops tegra_clk_m_ops = {
276 .init = tegra2_clk_m_init,
277 .enable = tegra2_clk_m_enable,
278 .disable = tegra2_clk_m_disable,
279 };
280
281 /* super clock functions */
282 /* "super clocks" on tegra have two-stage muxes and a clock skipping
283 * super divider. We will ignore the clock skipping divider, since we
284 * can't lower the voltage when using the clock skip, but we can if we
285 * lower the PLL frequency.
286 */
287 static void tegra2_super_clk_init(struct clk *c)
288 {
289 u32 val;
290 int source;
291 int shift;
292 const struct clk_mux_sel *sel;
293 val = clk_readl(c->reg + SUPER_CLK_MUX);
294 c->state = ON;
295 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
296 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
297 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
298 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
299 source = (val >> shift) & SUPER_SOURCE_MASK;
300 for (sel = c->inputs; sel->input != NULL; sel++) {
301 if (sel->value == source)
302 break;
303 }
304 BUG_ON(sel->input == NULL);
305 c->parent = sel->input;
306 }
307
308 static int tegra2_super_clk_enable(struct clk *c)
309 {
310 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
311 return 0;
312 }
313
314 static void tegra2_super_clk_disable(struct clk *c)
315 {
316 pr_debug("%s on clock %s\n", __func__, c->name);
317
318 /* oops - don't disable the CPU clock! */
319 BUG();
320 }
321
322 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
323 {
324 u32 val;
325 const struct clk_mux_sel *sel;
326 int shift;
327
328 val = clk_readl(c->reg + SUPER_CLK_MUX);
329 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
330 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
331 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
332 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
333 for (sel = c->inputs; sel->input != NULL; sel++) {
334 if (sel->input == p) {
335 val &= ~(SUPER_SOURCE_MASK << shift);
336 val |= sel->value << shift;
337
338 if (c->refcnt)
339 clk_enable(p);
340
341 clk_writel(val, c->reg);
342
343 if (c->refcnt && c->parent)
344 clk_disable(c->parent);
345
346 clk_reparent(c, p);
347 return 0;
348 }
349 }
350 return -EINVAL;
351 }
352
353 /*
354 * Super clocks have "clock skippers" instead of dividers. Dividing using
355 * a clock skipper does not allow the voltage to be scaled down, so instead
356 * adjust the rate of the parent clock. This requires that the parent of a
357 * super clock have no other children, otherwise the rate will change
358 * underneath the other children.
359 */
360 static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
361 {
362 return clk_set_rate(c->parent, rate);
363 }
364
365 static struct clk_ops tegra_super_ops = {
366 .init = tegra2_super_clk_init,
367 .enable = tegra2_super_clk_enable,
368 .disable = tegra2_super_clk_disable,
369 .set_parent = tegra2_super_clk_set_parent,
370 .set_rate = tegra2_super_clk_set_rate,
371 };
372
373 /* virtual cpu clock functions */
374 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
375 To change the frequency of these clocks, the parent pll may need to be
376 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
377 and then the clock moved back to the pll. To hide this sequence, a virtual
378 clock handles it.
379 */
380 static void tegra2_cpu_clk_init(struct clk *c)
381 {
382 }
383
384 static int tegra2_cpu_clk_enable(struct clk *c)
385 {
386 return 0;
387 }
388
389 static void tegra2_cpu_clk_disable(struct clk *c)
390 {
391 pr_debug("%s on clock %s\n", __func__, c->name);
392
393 /* oops - don't disable the CPU clock! */
394 BUG();
395 }
396
397 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
398 {
399 int ret;
400 /*
401 * Take an extra reference to the main pll so it doesn't turn
402 * off when we move the cpu off of it
403 */
404 clk_enable(c->u.cpu.main);
405
406 ret = clk_set_parent(c->parent, c->u.cpu.backup);
407 if (ret) {
408 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
409 goto out;
410 }
411
412 if (rate == clk_get_rate(c->u.cpu.backup))
413 goto out;
414
415 ret = clk_set_rate(c->u.cpu.main, rate);
416 if (ret) {
417 pr_err("Failed to change cpu pll to %lu\n", rate);
418 goto out;
419 }
420
421 ret = clk_set_parent(c->parent, c->u.cpu.main);
422 if (ret) {
423 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
424 goto out;
425 }
426
427 out:
428 clk_disable(c->u.cpu.main);
429 return ret;
430 }
431
432 static struct clk_ops tegra_cpu_ops = {
433 .init = tegra2_cpu_clk_init,
434 .enable = tegra2_cpu_clk_enable,
435 .disable = tegra2_cpu_clk_disable,
436 .set_rate = tegra2_cpu_clk_set_rate,
437 };
438
439 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
440 * reset the COP block (i.e. AVP) */
441 static void tegra2_cop_clk_reset(struct clk *c, bool assert)
442 {
443 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
444
445 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
446 clk_writel(1 << 1, reg);
447 }
448
449 static struct clk_ops tegra_cop_ops = {
450 .reset = tegra2_cop_clk_reset,
451 };
452
453 /* bus clock functions */
454 static void tegra2_bus_clk_init(struct clk *c)
455 {
456 u32 val = clk_readl(c->reg);
457 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
458 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
459 c->mul = 1;
460 }
461
462 static int tegra2_bus_clk_enable(struct clk *c)
463 {
464 u32 val;
465 unsigned long flags;
466
467 spin_lock_irqsave(&clock_register_lock, flags);
468
469 val = clk_readl(c->reg);
470 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
471 clk_writel(val, c->reg);
472
473 spin_unlock_irqrestore(&clock_register_lock, flags);
474
475 return 0;
476 }
477
478 static void tegra2_bus_clk_disable(struct clk *c)
479 {
480 u32 val;
481 unsigned long flags;
482
483 spin_lock_irqsave(&clock_register_lock, flags);
484
485 val = clk_readl(c->reg);
486 val |= BUS_CLK_DISABLE << c->reg_shift;
487 clk_writel(val, c->reg);
488
489 spin_unlock_irqrestore(&clock_register_lock, flags);
490 }
491
492 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
493 {
494 u32 val;
495 unsigned long parent_rate = clk_get_rate(c->parent);
496 unsigned long flags;
497 int ret = -EINVAL;
498 int i;
499
500 spin_lock_irqsave(&clock_register_lock, flags);
501
502 val = clk_readl(c->reg);
503 for (i = 1; i <= 4; i++) {
504 if (rate == parent_rate / i) {
505 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
506 val |= (i - 1) << c->reg_shift;
507 clk_writel(val, c->reg);
508 c->div = i;
509 c->mul = 1;
510 ret = 0;
511 break;
512 }
513 }
514
515 spin_unlock_irqrestore(&clock_register_lock, flags);
516
517 return ret;
518 }
519
520 static struct clk_ops tegra_bus_ops = {
521 .init = tegra2_bus_clk_init,
522 .enable = tegra2_bus_clk_enable,
523 .disable = tegra2_bus_clk_disable,
524 .set_rate = tegra2_bus_clk_set_rate,
525 };
526
527 /* Blink output functions */
528
529 static void tegra2_blink_clk_init(struct clk *c)
530 {
531 u32 val;
532
533 val = pmc_readl(PMC_CTRL);
534 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
535 c->mul = 1;
536 val = pmc_readl(c->reg);
537
538 if (val & PMC_BLINK_TIMER_ENB) {
539 unsigned int on_off;
540
541 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
542 PMC_BLINK_TIMER_DATA_ON_MASK;
543 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
544 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
545 on_off += val;
546 /* each tick in the blink timer is 4 32KHz clocks */
547 c->div = on_off * 4;
548 } else {
549 c->div = 1;
550 }
551 }
552
553 static int tegra2_blink_clk_enable(struct clk *c)
554 {
555 u32 val;
556
557 val = pmc_readl(PMC_DPD_PADS_ORIDE);
558 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
559
560 val = pmc_readl(PMC_CTRL);
561 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
562
563 return 0;
564 }
565
566 static void tegra2_blink_clk_disable(struct clk *c)
567 {
568 u32 val;
569
570 val = pmc_readl(PMC_CTRL);
571 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
572
573 val = pmc_readl(PMC_DPD_PADS_ORIDE);
574 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
575 }
576
577 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
578 {
579 unsigned long parent_rate = clk_get_rate(c->parent);
580 if (rate >= parent_rate) {
581 c->div = 1;
582 pmc_writel(0, c->reg);
583 } else {
584 unsigned int on_off;
585 u32 val;
586
587 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
588 c->div = on_off * 8;
589
590 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
591 PMC_BLINK_TIMER_DATA_ON_SHIFT;
592 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
593 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
594 val |= on_off;
595 val |= PMC_BLINK_TIMER_ENB;
596 pmc_writel(val, c->reg);
597 }
598
599 return 0;
600 }
601
602 static struct clk_ops tegra_blink_clk_ops = {
603 .init = &tegra2_blink_clk_init,
604 .enable = &tegra2_blink_clk_enable,
605 .disable = &tegra2_blink_clk_disable,
606 .set_rate = &tegra2_blink_clk_set_rate,
607 };
608
609 /* PLL Functions */
610 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
611 {
612 udelay(c->u.pll.lock_delay);
613
614 return 0;
615 }
616
617 static void tegra2_pll_clk_init(struct clk *c)
618 {
619 u32 val = clk_readl(c->reg + PLL_BASE);
620
621 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
622
623 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
624 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
625 c->mul = 1;
626 c->div = 1;
627 } else if (val & PLL_BASE_BYPASS) {
628 c->mul = 1;
629 c->div = 1;
630 } else {
631 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
632 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
633 if (c->flags & PLLU)
634 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
635 else
636 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
637 }
638 }
639
640 static int tegra2_pll_clk_enable(struct clk *c)
641 {
642 u32 val;
643 pr_debug("%s on clock %s\n", __func__, c->name);
644
645 val = clk_readl(c->reg + PLL_BASE);
646 val &= ~PLL_BASE_BYPASS;
647 val |= PLL_BASE_ENABLE;
648 clk_writel(val, c->reg + PLL_BASE);
649
650 tegra2_pll_clk_wait_for_lock(c);
651
652 return 0;
653 }
654
655 static void tegra2_pll_clk_disable(struct clk *c)
656 {
657 u32 val;
658 pr_debug("%s on clock %s\n", __func__, c->name);
659
660 val = clk_readl(c->reg);
661 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
662 clk_writel(val, c->reg);
663 }
664
665 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
666 {
667 u32 val;
668 unsigned long input_rate;
669 const struct clk_pll_freq_table *sel;
670
671 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
672
673 input_rate = clk_get_rate(c->parent);
674 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
675 if (sel->input_rate == input_rate && sel->output_rate == rate) {
676 c->mul = sel->n;
677 c->div = sel->m * sel->p;
678
679 val = clk_readl(c->reg + PLL_BASE);
680 if (c->flags & PLL_FIXED)
681 val |= PLL_BASE_OVERRIDE;
682 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
683 PLL_BASE_DIVM_MASK);
684 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
685 (sel->n << PLL_BASE_DIVN_SHIFT);
686 BUG_ON(sel->p < 1 || sel->p > 2);
687 if (c->flags & PLLU) {
688 if (sel->p == 1)
689 val |= PLLU_BASE_POST_DIV;
690 } else {
691 if (sel->p == 2)
692 val |= 1 << PLL_BASE_DIVP_SHIFT;
693 }
694 clk_writel(val, c->reg + PLL_BASE);
695
696 if (c->flags & PLL_HAS_CPCON) {
697 val = clk_readl(c->reg + PLL_MISC(c));
698 val &= ~PLL_MISC_CPCON_MASK;
699 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
700 clk_writel(val, c->reg + PLL_MISC(c));
701 }
702
703 if (c->state == ON)
704 tegra2_pll_clk_enable(c);
705
706 return 0;
707 }
708 }
709 return -EINVAL;
710 }
711
712 static struct clk_ops tegra_pll_ops = {
713 .init = tegra2_pll_clk_init,
714 .enable = tegra2_pll_clk_enable,
715 .disable = tegra2_pll_clk_disable,
716 .set_rate = tegra2_pll_clk_set_rate,
717 };
718
719 static void tegra2_pllx_clk_init(struct clk *c)
720 {
721 tegra2_pll_clk_init(c);
722
723 if (tegra_sku_id() == 7)
724 c->max_rate = 750000000;
725 }
726
727 static struct clk_ops tegra_pllx_ops = {
728 .init = tegra2_pllx_clk_init,
729 .enable = tegra2_pll_clk_enable,
730 .disable = tegra2_pll_clk_disable,
731 .set_rate = tegra2_pll_clk_set_rate,
732 };
733
734 static int tegra2_plle_clk_enable(struct clk *c)
735 {
736 u32 val;
737
738 pr_debug("%s on clock %s\n", __func__, c->name);
739
740 mdelay(1);
741
742 val = clk_readl(c->reg + PLL_BASE);
743 if (!(val & PLLE_MISC_READY))
744 return -EBUSY;
745
746 val = clk_readl(c->reg + PLL_BASE);
747 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
748 clk_writel(val, c->reg + PLL_BASE);
749
750 return 0;
751 }
752
753 static struct clk_ops tegra_plle_ops = {
754 .init = tegra2_pll_clk_init,
755 .enable = tegra2_plle_clk_enable,
756 .set_rate = tegra2_pll_clk_set_rate,
757 };
758
759 /* Clock divider ops */
760 static void tegra2_pll_div_clk_init(struct clk *c)
761 {
762 u32 val = clk_readl(c->reg);
763 u32 divu71;
764 val >>= c->reg_shift;
765 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
766 if (!(val & PLL_OUT_RESET_DISABLE))
767 c->state = OFF;
768
769 if (c->flags & DIV_U71) {
770 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
771 c->div = (divu71 + 2);
772 c->mul = 2;
773 } else if (c->flags & DIV_2) {
774 c->div = 2;
775 c->mul = 1;
776 } else {
777 c->div = 1;
778 c->mul = 1;
779 }
780 }
781
782 static int tegra2_pll_div_clk_enable(struct clk *c)
783 {
784 u32 val;
785 u32 new_val;
786 unsigned long flags;
787
788 pr_debug("%s: %s\n", __func__, c->name);
789 if (c->flags & DIV_U71) {
790 spin_lock_irqsave(&clock_register_lock, flags);
791 val = clk_readl(c->reg);
792 new_val = val >> c->reg_shift;
793 new_val &= 0xFFFF;
794
795 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
796
797 val &= ~(0xFFFF << c->reg_shift);
798 val |= new_val << c->reg_shift;
799 clk_writel(val, c->reg);
800 spin_unlock_irqrestore(&clock_register_lock, flags);
801 return 0;
802 } else if (c->flags & DIV_2) {
803 BUG_ON(!(c->flags & PLLD));
804 spin_lock_irqsave(&clock_register_lock, flags);
805 val = clk_readl(c->reg);
806 val &= ~PLLD_MISC_DIV_RST;
807 clk_writel(val, c->reg);
808 spin_unlock_irqrestore(&clock_register_lock, flags);
809 return 0;
810 }
811 return -EINVAL;
812 }
813
814 static void tegra2_pll_div_clk_disable(struct clk *c)
815 {
816 u32 val;
817 u32 new_val;
818 unsigned long flags;
819
820 pr_debug("%s: %s\n", __func__, c->name);
821 if (c->flags & DIV_U71) {
822 spin_lock_irqsave(&clock_register_lock, flags);
823 val = clk_readl(c->reg);
824 new_val = val >> c->reg_shift;
825 new_val &= 0xFFFF;
826
827 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
828
829 val &= ~(0xFFFF << c->reg_shift);
830 val |= new_val << c->reg_shift;
831 clk_writel(val, c->reg);
832 spin_unlock_irqrestore(&clock_register_lock, flags);
833 } else if (c->flags & DIV_2) {
834 BUG_ON(!(c->flags & PLLD));
835 spin_lock_irqsave(&clock_register_lock, flags);
836 val = clk_readl(c->reg);
837 val |= PLLD_MISC_DIV_RST;
838 clk_writel(val, c->reg);
839 spin_unlock_irqrestore(&clock_register_lock, flags);
840 }
841 }
842
843 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
844 {
845 u32 val;
846 u32 new_val;
847 int divider_u71;
848 unsigned long parent_rate = clk_get_rate(c->parent);
849 unsigned long flags;
850
851 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
852 if (c->flags & DIV_U71) {
853 divider_u71 = clk_div71_get_divider(parent_rate, rate);
854 if (divider_u71 >= 0) {
855 spin_lock_irqsave(&clock_register_lock, flags);
856 val = clk_readl(c->reg);
857 new_val = val >> c->reg_shift;
858 new_val &= 0xFFFF;
859 if (c->flags & DIV_U71_FIXED)
860 new_val |= PLL_OUT_OVERRIDE;
861 new_val &= ~PLL_OUT_RATIO_MASK;
862 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
863
864 val &= ~(0xFFFF << c->reg_shift);
865 val |= new_val << c->reg_shift;
866 clk_writel(val, c->reg);
867 c->div = divider_u71 + 2;
868 c->mul = 2;
869 spin_unlock_irqrestore(&clock_register_lock, flags);
870 return 0;
871 }
872 } else if (c->flags & DIV_2) {
873 if (parent_rate == rate * 2)
874 return 0;
875 }
876 return -EINVAL;
877 }
878
879 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
880 {
881 int divider;
882 unsigned long parent_rate = clk_get_rate(c->parent);
883 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
884
885 if (c->flags & DIV_U71) {
886 divider = clk_div71_get_divider(parent_rate, rate);
887 if (divider < 0)
888 return divider;
889 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
890 } else if (c->flags & DIV_2) {
891 return DIV_ROUND_UP(parent_rate, 2);
892 }
893 return -EINVAL;
894 }
895
896 static struct clk_ops tegra_pll_div_ops = {
897 .init = tegra2_pll_div_clk_init,
898 .enable = tegra2_pll_div_clk_enable,
899 .disable = tegra2_pll_div_clk_disable,
900 .set_rate = tegra2_pll_div_clk_set_rate,
901 .round_rate = tegra2_pll_div_clk_round_rate,
902 };
903
904 /* Periph clk ops */
905
906 static void tegra2_periph_clk_init(struct clk *c)
907 {
908 u32 val = clk_readl(c->reg);
909 const struct clk_mux_sel *mux = NULL;
910 const struct clk_mux_sel *sel;
911 if (c->flags & MUX) {
912 for (sel = c->inputs; sel->input != NULL; sel++) {
913 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
914 mux = sel;
915 }
916 BUG_ON(!mux);
917
918 c->parent = mux->input;
919 } else {
920 c->parent = c->inputs[0].input;
921 }
922
923 if (c->flags & DIV_U71) {
924 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
925 c->div = divu71 + 2;
926 c->mul = 2;
927 } else if (c->flags & DIV_U16) {
928 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
929 c->div = divu16 + 1;
930 c->mul = 1;
931 } else {
932 c->div = 1;
933 c->mul = 1;
934 }
935
936 c->state = ON;
937
938 if (!c->u.periph.clk_num)
939 return;
940
941 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
942 PERIPH_CLK_TO_ENB_BIT(c)))
943 c->state = OFF;
944
945 if (!(c->flags & PERIPH_NO_RESET))
946 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
947 PERIPH_CLK_TO_ENB_BIT(c))
948 c->state = OFF;
949 }
950
951 static int tegra2_periph_clk_enable(struct clk *c)
952 {
953 u32 val;
954 unsigned long flags;
955 int refcount;
956 pr_debug("%s on clock %s\n", __func__, c->name);
957
958 if (!c->u.periph.clk_num)
959 return 0;
960
961 spin_lock_irqsave(&clock_register_lock, flags);
962
963 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
964
965 if (refcount > 1)
966 goto out;
967
968 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
969 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
970 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
971 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
972 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
973 if (c->flags & PERIPH_EMC_ENB) {
974 /* The EMC peripheral clock has 2 extra enable bits */
975 /* FIXME: Do they need to be disabled? */
976 val = clk_readl(c->reg);
977 val |= 0x3 << 24;
978 clk_writel(val, c->reg);
979 }
980
981 out:
982 spin_unlock_irqrestore(&clock_register_lock, flags);
983
984 return 0;
985 }
986
987 static void tegra2_periph_clk_disable(struct clk *c)
988 {
989 unsigned long flags;
990
991 pr_debug("%s on clock %s\n", __func__, c->name);
992
993 if (!c->u.periph.clk_num)
994 return;
995
996 spin_lock_irqsave(&clock_register_lock, flags);
997
998 if (c->refcnt)
999 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1000
1001 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
1002 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1003 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1004
1005 spin_unlock_irqrestore(&clock_register_lock, flags);
1006 }
1007
1008 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1009 {
1010 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1011
1012 pr_debug("%s %s on clock %s\n", __func__,
1013 assert ? "assert" : "deassert", c->name);
1014
1015 BUG_ON(!c->u.periph.clk_num);
1016
1017 if (!(c->flags & PERIPH_NO_RESET))
1018 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1019 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1020 }
1021
1022 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1023 {
1024 u32 val;
1025 const struct clk_mux_sel *sel;
1026 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1027 for (sel = c->inputs; sel->input != NULL; sel++) {
1028 if (sel->input == p) {
1029 val = clk_readl(c->reg);
1030 val &= ~PERIPH_CLK_SOURCE_MASK;
1031 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
1032
1033 if (c->refcnt)
1034 clk_enable(p);
1035
1036 clk_writel(val, c->reg);
1037
1038 if (c->refcnt && c->parent)
1039 clk_disable(c->parent);
1040
1041 clk_reparent(c, p);
1042 return 0;
1043 }
1044 }
1045
1046 return -EINVAL;
1047 }
1048
1049 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1050 {
1051 u32 val;
1052 int divider;
1053 unsigned long parent_rate = clk_get_rate(c->parent);
1054
1055 if (c->flags & DIV_U71) {
1056 divider = clk_div71_get_divider(parent_rate, rate);
1057 if (divider >= 0) {
1058 val = clk_readl(c->reg);
1059 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1060 val |= divider;
1061 clk_writel(val, c->reg);
1062 c->div = divider + 2;
1063 c->mul = 2;
1064 return 0;
1065 }
1066 } else if (c->flags & DIV_U16) {
1067 divider = clk_div16_get_divider(parent_rate, rate);
1068 if (divider >= 0) {
1069 val = clk_readl(c->reg);
1070 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1071 val |= divider;
1072 clk_writel(val, c->reg);
1073 c->div = divider + 1;
1074 c->mul = 1;
1075 return 0;
1076 }
1077 } else if (parent_rate <= rate) {
1078 c->div = 1;
1079 c->mul = 1;
1080 return 0;
1081 }
1082 return -EINVAL;
1083 }
1084
1085 static long tegra2_periph_clk_round_rate(struct clk *c,
1086 unsigned long rate)
1087 {
1088 int divider;
1089 unsigned long parent_rate = clk_get_rate(c->parent);
1090 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1091
1092 if (c->flags & DIV_U71) {
1093 divider = clk_div71_get_divider(parent_rate, rate);
1094 if (divider < 0)
1095 return divider;
1096
1097 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1098 } else if (c->flags & DIV_U16) {
1099 divider = clk_div16_get_divider(parent_rate, rate);
1100 if (divider < 0)
1101 return divider;
1102 return DIV_ROUND_UP(parent_rate, divider + 1);
1103 }
1104 return -EINVAL;
1105 }
1106
1107 static struct clk_ops tegra_periph_clk_ops = {
1108 .init = &tegra2_periph_clk_init,
1109 .enable = &tegra2_periph_clk_enable,
1110 .disable = &tegra2_periph_clk_disable,
1111 .set_parent = &tegra2_periph_clk_set_parent,
1112 .set_rate = &tegra2_periph_clk_set_rate,
1113 .round_rate = &tegra2_periph_clk_round_rate,
1114 .reset = &tegra2_periph_clk_reset,
1115 };
1116
1117 /* The SDMMC controllers have extra bits in the clock source register that
1118 * adjust the delay between the clock and data to compenstate for delays
1119 * on the PCB. */
1120 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1121 {
1122 u32 reg;
1123 unsigned long flags;
1124
1125 spin_lock_irqsave(&c->spinlock, flags);
1126
1127 delay = clamp(delay, 0, 15);
1128 reg = clk_readl(c->reg);
1129 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1130 reg |= SDMMC_CLK_INT_FB_SEL;
1131 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1132 clk_writel(reg, c->reg);
1133
1134 spin_unlock_irqrestore(&c->spinlock, flags);
1135 }
1136
1137 /* External memory controller clock ops */
1138 static void tegra2_emc_clk_init(struct clk *c)
1139 {
1140 tegra2_periph_clk_init(c);
1141 c->max_rate = clk_get_rate_locked(c);
1142 }
1143
1144 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1145 {
1146 long new_rate = rate;
1147
1148 new_rate = tegra_emc_round_rate(new_rate);
1149 if (new_rate < 0)
1150 return c->max_rate;
1151
1152 BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate));
1153
1154 return new_rate;
1155 }
1156
1157 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1158 {
1159 int ret;
1160 /*
1161 * The Tegra2 memory controller has an interlock with the clock
1162 * block that allows memory shadowed registers to be updated,
1163 * and then transfer them to the main registers at the same
1164 * time as the clock update without glitches.
1165 */
1166 ret = tegra_emc_set_rate(rate);
1167 if (ret < 0)
1168 return ret;
1169
1170 ret = tegra2_periph_clk_set_rate(c, rate);
1171 udelay(1);
1172
1173 return ret;
1174 }
1175
1176 static struct clk_ops tegra_emc_clk_ops = {
1177 .init = &tegra2_emc_clk_init,
1178 .enable = &tegra2_periph_clk_enable,
1179 .disable = &tegra2_periph_clk_disable,
1180 .set_parent = &tegra2_periph_clk_set_parent,
1181 .set_rate = &tegra2_emc_clk_set_rate,
1182 .round_rate = &tegra2_emc_clk_round_rate,
1183 .reset = &tegra2_periph_clk_reset,
1184 };
1185
1186 /* Clock doubler ops */
1187 static void tegra2_clk_double_init(struct clk *c)
1188 {
1189 c->mul = 2;
1190 c->div = 1;
1191 c->state = ON;
1192
1193 if (!c->u.periph.clk_num)
1194 return;
1195
1196 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1197 PERIPH_CLK_TO_ENB_BIT(c)))
1198 c->state = OFF;
1199 };
1200
1201 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1202 {
1203 if (rate != 2 * clk_get_rate(c->parent))
1204 return -EINVAL;
1205 c->mul = 2;
1206 c->div = 1;
1207 return 0;
1208 }
1209
1210 static struct clk_ops tegra_clk_double_ops = {
1211 .init = &tegra2_clk_double_init,
1212 .enable = &tegra2_periph_clk_enable,
1213 .disable = &tegra2_periph_clk_disable,
1214 .set_rate = &tegra2_clk_double_set_rate,
1215 };
1216
1217 /* Audio sync clock ops */
1218 static void tegra2_audio_sync_clk_init(struct clk *c)
1219 {
1220 int source;
1221 const struct clk_mux_sel *sel;
1222 u32 val = clk_readl(c->reg);
1223 c->state = (val & (1<<4)) ? OFF : ON;
1224 source = val & 0xf;
1225 for (sel = c->inputs; sel->input != NULL; sel++)
1226 if (sel->value == source)
1227 break;
1228 BUG_ON(sel->input == NULL);
1229 c->parent = sel->input;
1230 }
1231
1232 static int tegra2_audio_sync_clk_enable(struct clk *c)
1233 {
1234 clk_writel(0, c->reg);
1235 return 0;
1236 }
1237
1238 static void tegra2_audio_sync_clk_disable(struct clk *c)
1239 {
1240 clk_writel(1, c->reg);
1241 }
1242
1243 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1244 {
1245 u32 val;
1246 const struct clk_mux_sel *sel;
1247 for (sel = c->inputs; sel->input != NULL; sel++) {
1248 if (sel->input == p) {
1249 val = clk_readl(c->reg);
1250 val &= ~0xf;
1251 val |= sel->value;
1252
1253 if (c->refcnt)
1254 clk_enable(p);
1255
1256 clk_writel(val, c->reg);
1257
1258 if (c->refcnt && c->parent)
1259 clk_disable(c->parent);
1260
1261 clk_reparent(c, p);
1262 return 0;
1263 }
1264 }
1265
1266 return -EINVAL;
1267 }
1268
1269 static struct clk_ops tegra_audio_sync_clk_ops = {
1270 .init = tegra2_audio_sync_clk_init,
1271 .enable = tegra2_audio_sync_clk_enable,
1272 .disable = tegra2_audio_sync_clk_disable,
1273 .set_parent = tegra2_audio_sync_clk_set_parent,
1274 };
1275
1276 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1277
1278 static void tegra2_cdev_clk_init(struct clk *c)
1279 {
1280 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1281 * currently done in the pinmux code. */
1282 c->state = ON;
1283
1284 BUG_ON(!c->u.periph.clk_num);
1285
1286 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1287 PERIPH_CLK_TO_ENB_BIT(c)))
1288 c->state = OFF;
1289 }
1290
1291 static int tegra2_cdev_clk_enable(struct clk *c)
1292 {
1293 BUG_ON(!c->u.periph.clk_num);
1294
1295 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1296 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1297 return 0;
1298 }
1299
1300 static void tegra2_cdev_clk_disable(struct clk *c)
1301 {
1302 BUG_ON(!c->u.periph.clk_num);
1303
1304 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1305 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1306 }
1307
1308 static struct clk_ops tegra_cdev_clk_ops = {
1309 .init = &tegra2_cdev_clk_init,
1310 .enable = &tegra2_cdev_clk_enable,
1311 .disable = &tegra2_cdev_clk_disable,
1312 };
1313
1314 /* shared bus ops */
1315 /*
1316 * Some clocks may have multiple downstream users that need to request a
1317 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1318 * clock to each user. The frequency of the bus is set to the highest
1319 * enabled shared_bus_user clock, with a minimum value set by the
1320 * shared bus.
1321 */
1322 static int tegra_clk_shared_bus_update(struct clk *bus)
1323 {
1324 struct clk *c;
1325 unsigned long rate = bus->min_rate;
1326
1327 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1328 if (c->u.shared_bus_user.enabled)
1329 rate = max(c->u.shared_bus_user.rate, rate);
1330
1331 if (rate == clk_get_rate_locked(bus))
1332 return 0;
1333
1334 return clk_set_rate_locked(bus, rate);
1335 };
1336
1337 static void tegra_clk_shared_bus_init(struct clk *c)
1338 {
1339 unsigned long flags;
1340
1341 c->max_rate = c->parent->max_rate;
1342 c->u.shared_bus_user.rate = c->parent->max_rate;
1343 c->state = OFF;
1344 c->set = true;
1345
1346 spin_lock_irqsave(&c->parent->spinlock, flags);
1347
1348 list_add_tail(&c->u.shared_bus_user.node,
1349 &c->parent->shared_bus_list);
1350
1351 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1352 }
1353
1354 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1355 {
1356 unsigned long flags;
1357 int ret;
1358 long new_rate = rate;
1359
1360 new_rate = clk_round_rate(c->parent, new_rate);
1361 if (new_rate < 0)
1362 return new_rate;
1363
1364 spin_lock_irqsave(&c->parent->spinlock, flags);
1365
1366 c->u.shared_bus_user.rate = new_rate;
1367 ret = tegra_clk_shared_bus_update(c->parent);
1368
1369 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1370
1371 return ret;
1372 }
1373
1374 static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1375 {
1376 return clk_round_rate(c->parent, rate);
1377 }
1378
1379 static int tegra_clk_shared_bus_enable(struct clk *c)
1380 {
1381 unsigned long flags;
1382 int ret;
1383
1384 spin_lock_irqsave(&c->parent->spinlock, flags);
1385
1386 c->u.shared_bus_user.enabled = true;
1387 ret = tegra_clk_shared_bus_update(c->parent);
1388
1389 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1390
1391 return ret;
1392 }
1393
1394 static void tegra_clk_shared_bus_disable(struct clk *c)
1395 {
1396 unsigned long flags;
1397 int ret;
1398
1399 spin_lock_irqsave(&c->parent->spinlock, flags);
1400
1401 c->u.shared_bus_user.enabled = false;
1402 ret = tegra_clk_shared_bus_update(c->parent);
1403 WARN_ON_ONCE(ret);
1404
1405 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1406 }
1407
1408 static struct clk_ops tegra_clk_shared_bus_ops = {
1409 .init = tegra_clk_shared_bus_init,
1410 .enable = tegra_clk_shared_bus_enable,
1411 .disable = tegra_clk_shared_bus_disable,
1412 .set_rate = tegra_clk_shared_bus_set_rate,
1413 .round_rate = tegra_clk_shared_bus_round_rate,
1414 };
1415
1416
1417 /* Clock definitions */
1418 static struct clk tegra_clk_32k = {
1419 .name = "clk_32k",
1420 .rate = 32768,
1421 .ops = NULL,
1422 .max_rate = 32768,
1423 };
1424
1425 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1426 {32768, 12000000, 366, 1, 1, 0},
1427 {32768, 13000000, 397, 1, 1, 0},
1428 {32768, 19200000, 586, 1, 1, 0},
1429 {32768, 26000000, 793, 1, 1, 0},
1430 {0, 0, 0, 0, 0, 0},
1431 };
1432
1433 static struct clk tegra_pll_s = {
1434 .name = "pll_s",
1435 .flags = PLL_ALT_MISC_REG,
1436 .ops = &tegra_pll_ops,
1437 .parent = &tegra_clk_32k,
1438 .max_rate = 26000000,
1439 .reg = 0xf0,
1440 .u.pll = {
1441 .input_min = 32768,
1442 .input_max = 32768,
1443 .cf_min = 0, /* FIXME */
1444 .cf_max = 0, /* FIXME */
1445 .vco_min = 12000000,
1446 .vco_max = 26000000,
1447 .freq_table = tegra_pll_s_freq_table,
1448 .lock_delay = 300,
1449 },
1450 };
1451
1452 static struct clk_mux_sel tegra_clk_m_sel[] = {
1453 { .input = &tegra_clk_32k, .value = 0},
1454 { .input = &tegra_pll_s, .value = 1},
1455 { NULL , 0},
1456 };
1457
1458 static struct clk tegra_clk_m = {
1459 .name = "clk_m",
1460 .flags = ENABLE_ON_INIT,
1461 .ops = &tegra_clk_m_ops,
1462 .inputs = tegra_clk_m_sel,
1463 .reg = 0x1fc,
1464 .reg_shift = 28,
1465 .max_rate = 26000000,
1466 };
1467
1468 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1469 { 0, 0, 0, 0, 0, 0 },
1470 };
1471
1472 static struct clk tegra_pll_c = {
1473 .name = "pll_c",
1474 .flags = PLL_HAS_CPCON,
1475 .ops = &tegra_pll_ops,
1476 .reg = 0x80,
1477 .parent = &tegra_clk_m,
1478 .max_rate = 600000000,
1479 .u.pll = {
1480 .input_min = 2000000,
1481 .input_max = 31000000,
1482 .cf_min = 1000000,
1483 .cf_max = 6000000,
1484 .vco_min = 20000000,
1485 .vco_max = 1400000000,
1486 .freq_table = tegra_pll_c_freq_table,
1487 .lock_delay = 300,
1488 },
1489 };
1490
1491 static struct clk tegra_pll_c_out1 = {
1492 .name = "pll_c_out1",
1493 .ops = &tegra_pll_div_ops,
1494 .flags = DIV_U71,
1495 .parent = &tegra_pll_c,
1496 .reg = 0x84,
1497 .reg_shift = 0,
1498 .max_rate = 600000000,
1499 };
1500
1501 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1502 { 12000000, 666000000, 666, 12, 1, 8},
1503 { 13000000, 666000000, 666, 13, 1, 8},
1504 { 19200000, 666000000, 555, 16, 1, 8},
1505 { 26000000, 666000000, 666, 26, 1, 8},
1506 { 12000000, 600000000, 600, 12, 1, 8},
1507 { 13000000, 600000000, 600, 13, 1, 8},
1508 { 19200000, 600000000, 375, 12, 1, 6},
1509 { 26000000, 600000000, 600, 26, 1, 8},
1510 { 0, 0, 0, 0, 0, 0 },
1511 };
1512
1513 static struct clk tegra_pll_m = {
1514 .name = "pll_m",
1515 .flags = PLL_HAS_CPCON,
1516 .ops = &tegra_pll_ops,
1517 .reg = 0x90,
1518 .parent = &tegra_clk_m,
1519 .max_rate = 800000000,
1520 .u.pll = {
1521 .input_min = 2000000,
1522 .input_max = 31000000,
1523 .cf_min = 1000000,
1524 .cf_max = 6000000,
1525 .vco_min = 20000000,
1526 .vco_max = 1200000000,
1527 .freq_table = tegra_pll_m_freq_table,
1528 .lock_delay = 300,
1529 },
1530 };
1531
1532 static struct clk tegra_pll_m_out1 = {
1533 .name = "pll_m_out1",
1534 .ops = &tegra_pll_div_ops,
1535 .flags = DIV_U71,
1536 .parent = &tegra_pll_m,
1537 .reg = 0x94,
1538 .reg_shift = 0,
1539 .max_rate = 600000000,
1540 };
1541
1542 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1543 { 12000000, 216000000, 432, 12, 2, 8},
1544 { 13000000, 216000000, 432, 13, 2, 8},
1545 { 19200000, 216000000, 90, 4, 2, 1},
1546 { 26000000, 216000000, 432, 26, 2, 8},
1547 { 12000000, 432000000, 432, 12, 1, 8},
1548 { 13000000, 432000000, 432, 13, 1, 8},
1549 { 19200000, 432000000, 90, 4, 1, 1},
1550 { 26000000, 432000000, 432, 26, 1, 8},
1551 { 0, 0, 0, 0, 0, 0 },
1552 };
1553
1554 static struct clk tegra_pll_p = {
1555 .name = "pll_p",
1556 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1557 .ops = &tegra_pll_ops,
1558 .reg = 0xa0,
1559 .parent = &tegra_clk_m,
1560 .max_rate = 432000000,
1561 .u.pll = {
1562 .input_min = 2000000,
1563 .input_max = 31000000,
1564 .cf_min = 1000000,
1565 .cf_max = 6000000,
1566 .vco_min = 20000000,
1567 .vco_max = 1400000000,
1568 .freq_table = tegra_pll_p_freq_table,
1569 .lock_delay = 300,
1570 },
1571 };
1572
1573 static struct clk tegra_pll_p_out1 = {
1574 .name = "pll_p_out1",
1575 .ops = &tegra_pll_div_ops,
1576 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1577 .parent = &tegra_pll_p,
1578 .reg = 0xa4,
1579 .reg_shift = 0,
1580 .max_rate = 432000000,
1581 };
1582
1583 static struct clk tegra_pll_p_out2 = {
1584 .name = "pll_p_out2",
1585 .ops = &tegra_pll_div_ops,
1586 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1587 .parent = &tegra_pll_p,
1588 .reg = 0xa4,
1589 .reg_shift = 16,
1590 .max_rate = 432000000,
1591 };
1592
1593 static struct clk tegra_pll_p_out3 = {
1594 .name = "pll_p_out3",
1595 .ops = &tegra_pll_div_ops,
1596 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1597 .parent = &tegra_pll_p,
1598 .reg = 0xa8,
1599 .reg_shift = 0,
1600 .max_rate = 432000000,
1601 };
1602
1603 static struct clk tegra_pll_p_out4 = {
1604 .name = "pll_p_out4",
1605 .ops = &tegra_pll_div_ops,
1606 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1607 .parent = &tegra_pll_p,
1608 .reg = 0xa8,
1609 .reg_shift = 16,
1610 .max_rate = 432000000,
1611 };
1612
1613 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1614 { 28800000, 56448000, 49, 25, 1, 1},
1615 { 28800000, 73728000, 64, 25, 1, 1},
1616 { 28800000, 24000000, 5, 6, 1, 1},
1617 { 0, 0, 0, 0, 0, 0 },
1618 };
1619
1620 static struct clk tegra_pll_a = {
1621 .name = "pll_a",
1622 .flags = PLL_HAS_CPCON,
1623 .ops = &tegra_pll_ops,
1624 .reg = 0xb0,
1625 .parent = &tegra_pll_p_out1,
1626 .max_rate = 73728000,
1627 .u.pll = {
1628 .input_min = 2000000,
1629 .input_max = 31000000,
1630 .cf_min = 1000000,
1631 .cf_max = 6000000,
1632 .vco_min = 20000000,
1633 .vco_max = 1400000000,
1634 .freq_table = tegra_pll_a_freq_table,
1635 .lock_delay = 300,
1636 },
1637 };
1638
1639 static struct clk tegra_pll_a_out0 = {
1640 .name = "pll_a_out0",
1641 .ops = &tegra_pll_div_ops,
1642 .flags = DIV_U71,
1643 .parent = &tegra_pll_a,
1644 .reg = 0xb4,
1645 .reg_shift = 0,
1646 .max_rate = 73728000,
1647 };
1648
1649 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1650 { 12000000, 216000000, 216, 12, 1, 4},
1651 { 13000000, 216000000, 216, 13, 1, 4},
1652 { 19200000, 216000000, 135, 12, 1, 3},
1653 { 26000000, 216000000, 216, 26, 1, 4},
1654
1655 { 12000000, 594000000, 594, 12, 1, 8},
1656 { 13000000, 594000000, 594, 13, 1, 8},
1657 { 19200000, 594000000, 495, 16, 1, 8},
1658 { 26000000, 594000000, 594, 26, 1, 8},
1659
1660 { 12000000, 1000000000, 1000, 12, 1, 12},
1661 { 13000000, 1000000000, 1000, 13, 1, 12},
1662 { 19200000, 1000000000, 625, 12, 1, 8},
1663 { 26000000, 1000000000, 1000, 26, 1, 12},
1664
1665 { 0, 0, 0, 0, 0, 0 },
1666 };
1667
1668 static struct clk tegra_pll_d = {
1669 .name = "pll_d",
1670 .flags = PLL_HAS_CPCON | PLLD,
1671 .ops = &tegra_pll_ops,
1672 .reg = 0xd0,
1673 .parent = &tegra_clk_m,
1674 .max_rate = 1000000000,
1675 .u.pll = {
1676 .input_min = 2000000,
1677 .input_max = 40000000,
1678 .cf_min = 1000000,
1679 .cf_max = 6000000,
1680 .vco_min = 40000000,
1681 .vco_max = 1000000000,
1682 .freq_table = tegra_pll_d_freq_table,
1683 .lock_delay = 1000,
1684 },
1685 };
1686
1687 static struct clk tegra_pll_d_out0 = {
1688 .name = "pll_d_out0",
1689 .ops = &tegra_pll_div_ops,
1690 .flags = DIV_2 | PLLD,
1691 .parent = &tegra_pll_d,
1692 .max_rate = 500000000,
1693 };
1694
1695 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1696 { 12000000, 480000000, 960, 12, 2, 0},
1697 { 13000000, 480000000, 960, 13, 2, 0},
1698 { 19200000, 480000000, 200, 4, 2, 0},
1699 { 26000000, 480000000, 960, 26, 2, 0},
1700 { 0, 0, 0, 0, 0, 0 },
1701 };
1702
1703 static struct clk tegra_pll_u = {
1704 .name = "pll_u",
1705 .flags = PLLU,
1706 .ops = &tegra_pll_ops,
1707 .reg = 0xc0,
1708 .parent = &tegra_clk_m,
1709 .max_rate = 480000000,
1710 .u.pll = {
1711 .input_min = 2000000,
1712 .input_max = 40000000,
1713 .cf_min = 1000000,
1714 .cf_max = 6000000,
1715 .vco_min = 480000000,
1716 .vco_max = 960000000,
1717 .freq_table = tegra_pll_u_freq_table,
1718 .lock_delay = 1000,
1719 },
1720 };
1721
1722 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1723 /* 1 GHz */
1724 { 12000000, 1000000000, 1000, 12, 1, 12},
1725 { 13000000, 1000000000, 1000, 13, 1, 12},
1726 { 19200000, 1000000000, 625, 12, 1, 8},
1727 { 26000000, 1000000000, 1000, 26, 1, 12},
1728
1729 /* 912 MHz */
1730 { 12000000, 912000000, 912, 12, 1, 12},
1731 { 13000000, 912000000, 912, 13, 1, 12},
1732 { 19200000, 912000000, 760, 16, 1, 8},
1733 { 26000000, 912000000, 912, 26, 1, 12},
1734
1735 /* 816 MHz */
1736 { 12000000, 816000000, 816, 12, 1, 12},
1737 { 13000000, 816000000, 816, 13, 1, 12},
1738 { 19200000, 816000000, 680, 16, 1, 8},
1739 { 26000000, 816000000, 816, 26, 1, 12},
1740
1741 /* 760 MHz */
1742 { 12000000, 760000000, 760, 12, 1, 12},
1743 { 13000000, 760000000, 760, 13, 1, 12},
1744 { 19200000, 760000000, 950, 24, 1, 8},
1745 { 26000000, 760000000, 760, 26, 1, 12},
1746
1747 /* 608 MHz */
1748 { 12000000, 608000000, 608, 12, 1, 12},
1749 { 13000000, 608000000, 608, 13, 1, 12},
1750 { 19200000, 608000000, 380, 12, 1, 8},
1751 { 26000000, 608000000, 608, 26, 1, 12},
1752
1753 /* 456 MHz */
1754 { 12000000, 456000000, 456, 12, 1, 12},
1755 { 13000000, 456000000, 456, 13, 1, 12},
1756 { 19200000, 456000000, 380, 16, 1, 8},
1757 { 26000000, 456000000, 456, 26, 1, 12},
1758
1759 /* 312 MHz */
1760 { 12000000, 312000000, 312, 12, 1, 12},
1761 { 13000000, 312000000, 312, 13, 1, 12},
1762 { 19200000, 312000000, 260, 16, 1, 8},
1763 { 26000000, 312000000, 312, 26, 1, 12},
1764
1765 { 0, 0, 0, 0, 0, 0 },
1766 };
1767
1768 static struct clk tegra_pll_x = {
1769 .name = "pll_x",
1770 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1771 .ops = &tegra_pllx_ops,
1772 .reg = 0xe0,
1773 .parent = &tegra_clk_m,
1774 .max_rate = 1000000000,
1775 .u.pll = {
1776 .input_min = 2000000,
1777 .input_max = 31000000,
1778 .cf_min = 1000000,
1779 .cf_max = 6000000,
1780 .vco_min = 20000000,
1781 .vco_max = 1200000000,
1782 .freq_table = tegra_pll_x_freq_table,
1783 .lock_delay = 300,
1784 },
1785 };
1786
1787 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1788 { 12000000, 100000000, 200, 24, 1, 0 },
1789 { 0, 0, 0, 0, 0, 0 },
1790 };
1791
1792 static struct clk tegra_pll_e = {
1793 .name = "pll_e",
1794 .flags = PLL_ALT_MISC_REG,
1795 .ops = &tegra_plle_ops,
1796 .parent = &tegra_clk_m,
1797 .reg = 0xe8,
1798 .max_rate = 100000000,
1799 .u.pll = {
1800 .input_min = 12000000,
1801 .input_max = 12000000,
1802 .freq_table = tegra_pll_e_freq_table,
1803 },
1804 };
1805
1806 static struct clk tegra_clk_d = {
1807 .name = "clk_d",
1808 .flags = PERIPH_NO_RESET,
1809 .ops = &tegra_clk_double_ops,
1810 .reg = 0x34,
1811 .reg_shift = 12,
1812 .parent = &tegra_clk_m,
1813 .max_rate = 52000000,
1814 .u.periph = {
1815 .clk_num = 90,
1816 },
1817 };
1818
1819 /* dap_mclk1, belongs to the cdev1 pingroup. */
1820 static struct clk tegra_clk_cdev1 = {
1821 .name = "cdev1",
1822 .ops = &tegra_cdev_clk_ops,
1823 .rate = 26000000,
1824 .max_rate = 26000000,
1825 .u.periph = {
1826 .clk_num = 94,
1827 },
1828 };
1829
1830 /* dap_mclk2, belongs to the cdev2 pingroup. */
1831 static struct clk tegra_clk_cdev2 = {
1832 .name = "cdev2",
1833 .ops = &tegra_cdev_clk_ops,
1834 .rate = 26000000,
1835 .max_rate = 26000000,
1836 .u.periph = {
1837 .clk_num = 93,
1838 },
1839 };
1840
1841 /* initialized before peripheral clocks */
1842 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1843 static const struct audio_sources {
1844 const char *name;
1845 int value;
1846 } mux_audio_sync_clk_sources[] = {
1847 { .name = "spdif_in", .value = 0 },
1848 { .name = "i2s1", .value = 1 },
1849 { .name = "i2s2", .value = 2 },
1850 { .name = "pll_a_out0", .value = 4 },
1851 #if 0 /* FIXME: not implemented */
1852 { .name = "ac97", .value = 3 },
1853 { .name = "ext_audio_clk2", .value = 5 },
1854 { .name = "ext_audio_clk1", .value = 6 },
1855 { .name = "ext_vimclk", .value = 7 },
1856 #endif
1857 { NULL, 0 }
1858 };
1859
1860 static struct clk tegra_clk_audio = {
1861 .name = "audio",
1862 .inputs = mux_audio_sync_clk,
1863 .reg = 0x38,
1864 .max_rate = 73728000,
1865 .ops = &tegra_audio_sync_clk_ops
1866 };
1867
1868 static struct clk tegra_clk_audio_2x = {
1869 .name = "audio_2x",
1870 .flags = PERIPH_NO_RESET,
1871 .max_rate = 48000000,
1872 .ops = &tegra_clk_double_ops,
1873 .reg = 0x34,
1874 .reg_shift = 8,
1875 .parent = &tegra_clk_audio,
1876 .u.periph = {
1877 .clk_num = 89,
1878 },
1879 };
1880
1881 static struct clk_lookup tegra_audio_clk_lookups[] = {
1882 { .con_id = "audio", .clk = &tegra_clk_audio },
1883 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1884 };
1885
1886 /* This is called after peripheral clocks are initialized, as the
1887 * audio_sync clock depends on some of the peripheral clocks.
1888 */
1889
1890 static void init_audio_sync_clock_mux(void)
1891 {
1892 int i;
1893 struct clk_mux_sel *sel = mux_audio_sync_clk;
1894 const struct audio_sources *src = mux_audio_sync_clk_sources;
1895 struct clk_lookup *lookup;
1896
1897 for (i = 0; src->name; i++, sel++, src++) {
1898 sel->input = tegra_get_clock_by_name(src->name);
1899 if (!sel->input)
1900 pr_err("%s: could not find clk %s\n", __func__,
1901 src->name);
1902 sel->value = src->value;
1903 }
1904
1905 lookup = tegra_audio_clk_lookups;
1906 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1907 clk_init(lookup->clk);
1908 clkdev_add(lookup);
1909 }
1910 }
1911
1912 static struct clk_mux_sel mux_cclk[] = {
1913 { .input = &tegra_clk_m, .value = 0},
1914 { .input = &tegra_pll_c, .value = 1},
1915 { .input = &tegra_clk_32k, .value = 2},
1916 { .input = &tegra_pll_m, .value = 3},
1917 { .input = &tegra_pll_p, .value = 4},
1918 { .input = &tegra_pll_p_out4, .value = 5},
1919 { .input = &tegra_pll_p_out3, .value = 6},
1920 { .input = &tegra_clk_d, .value = 7},
1921 { .input = &tegra_pll_x, .value = 8},
1922 { NULL, 0},
1923 };
1924
1925 static struct clk_mux_sel mux_sclk[] = {
1926 { .input = &tegra_clk_m, .value = 0},
1927 { .input = &tegra_pll_c_out1, .value = 1},
1928 { .input = &tegra_pll_p_out4, .value = 2},
1929 { .input = &tegra_pll_p_out3, .value = 3},
1930 { .input = &tegra_pll_p_out2, .value = 4},
1931 { .input = &tegra_clk_d, .value = 5},
1932 { .input = &tegra_clk_32k, .value = 6},
1933 { .input = &tegra_pll_m_out1, .value = 7},
1934 { NULL, 0},
1935 };
1936
1937 static struct clk tegra_clk_cclk = {
1938 .name = "cclk",
1939 .inputs = mux_cclk,
1940 .reg = 0x20,
1941 .ops = &tegra_super_ops,
1942 .max_rate = 1000000000,
1943 };
1944
1945 static struct clk tegra_clk_sclk = {
1946 .name = "sclk",
1947 .inputs = mux_sclk,
1948 .reg = 0x28,
1949 .ops = &tegra_super_ops,
1950 .max_rate = 240000000,
1951 .min_rate = 120000000,
1952 };
1953
1954 static struct clk tegra_clk_virtual_cpu = {
1955 .name = "cpu",
1956 .parent = &tegra_clk_cclk,
1957 .ops = &tegra_cpu_ops,
1958 .max_rate = 1000000000,
1959 .u.cpu = {
1960 .main = &tegra_pll_x,
1961 .backup = &tegra_pll_p,
1962 },
1963 };
1964
1965 static struct clk tegra_clk_cop = {
1966 .name = "cop",
1967 .parent = &tegra_clk_sclk,
1968 .ops = &tegra_cop_ops,
1969 .max_rate = 240000000,
1970 };
1971
1972 static struct clk tegra_clk_hclk = {
1973 .name = "hclk",
1974 .flags = DIV_BUS,
1975 .parent = &tegra_clk_sclk,
1976 .reg = 0x30,
1977 .reg_shift = 4,
1978 .ops = &tegra_bus_ops,
1979 .max_rate = 240000000,
1980 };
1981
1982 static struct clk tegra_clk_pclk = {
1983 .name = "pclk",
1984 .flags = DIV_BUS,
1985 .parent = &tegra_clk_hclk,
1986 .reg = 0x30,
1987 .reg_shift = 0,
1988 .ops = &tegra_bus_ops,
1989 .max_rate = 120000000,
1990 };
1991
1992 static struct clk tegra_clk_blink = {
1993 .name = "blink",
1994 .parent = &tegra_clk_32k,
1995 .reg = 0x40,
1996 .ops = &tegra_blink_clk_ops,
1997 .max_rate = 32768,
1998 };
1999
2000 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2001 { .input = &tegra_pll_m, .value = 0},
2002 { .input = &tegra_pll_c, .value = 1},
2003 { .input = &tegra_pll_p, .value = 2},
2004 { .input = &tegra_pll_a_out0, .value = 3},
2005 { NULL, 0},
2006 };
2007
2008 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2009 { .input = &tegra_pll_m, .value = 0},
2010 { .input = &tegra_pll_c, .value = 1},
2011 { .input = &tegra_pll_p, .value = 2},
2012 { .input = &tegra_clk_m, .value = 3},
2013 { NULL, 0},
2014 };
2015
2016 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2017 { .input = &tegra_pll_p, .value = 0},
2018 { .input = &tegra_pll_c, .value = 1},
2019 { .input = &tegra_pll_m, .value = 2},
2020 { .input = &tegra_clk_m, .value = 3},
2021 { NULL, 0},
2022 };
2023
2024 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2025 {.input = &tegra_pll_a_out0, .value = 0},
2026 {.input = &tegra_clk_audio_2x, .value = 1},
2027 {.input = &tegra_pll_p, .value = 2},
2028 {.input = &tegra_clk_m, .value = 3},
2029 { NULL, 0},
2030 };
2031
2032 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2033 {.input = &tegra_pll_p, .value = 0},
2034 {.input = &tegra_pll_d_out0, .value = 1},
2035 {.input = &tegra_pll_c, .value = 2},
2036 {.input = &tegra_clk_m, .value = 3},
2037 { NULL, 0},
2038 };
2039
2040 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2041 {.input = &tegra_pll_p, .value = 0},
2042 {.input = &tegra_pll_c, .value = 1},
2043 {.input = &tegra_clk_audio, .value = 2},
2044 {.input = &tegra_clk_m, .value = 3},
2045 {.input = &tegra_clk_32k, .value = 4},
2046 { NULL, 0},
2047 };
2048
2049 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2050 {.input = &tegra_pll_p, .value = 0},
2051 {.input = &tegra_pll_c, .value = 1},
2052 {.input = &tegra_pll_m, .value = 2},
2053 { NULL, 0},
2054 };
2055
2056 static struct clk_mux_sel mux_clk_m[] = {
2057 { .input = &tegra_clk_m, .value = 0},
2058 { NULL, 0},
2059 };
2060
2061 static struct clk_mux_sel mux_pllp_out3[] = {
2062 { .input = &tegra_pll_p_out3, .value = 0},
2063 { NULL, 0},
2064 };
2065
2066 static struct clk_mux_sel mux_plld[] = {
2067 { .input = &tegra_pll_d, .value = 0},
2068 { NULL, 0},
2069 };
2070
2071 static struct clk_mux_sel mux_clk_32k[] = {
2072 { .input = &tegra_clk_32k, .value = 0},
2073 { NULL, 0},
2074 };
2075
2076 static struct clk_mux_sel mux_pclk[] = {
2077 { .input = &tegra_clk_pclk, .value = 0},
2078 { NULL, 0},
2079 };
2080
2081 static struct clk tegra_clk_emc = {
2082 .name = "emc",
2083 .ops = &tegra_emc_clk_ops,
2084 .reg = 0x19c,
2085 .max_rate = 800000000,
2086 .inputs = mux_pllm_pllc_pllp_clkm,
2087 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2088 .u.periph = {
2089 .clk_num = 57,
2090 },
2091 };
2092
2093 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2094 { \
2095 .name = _name, \
2096 .lookup = { \
2097 .dev_id = _dev, \
2098 .con_id = _con, \
2099 }, \
2100 .ops = &tegra_periph_clk_ops, \
2101 .reg = _reg, \
2102 .inputs = _inputs, \
2103 .flags = _flags, \
2104 .max_rate = _max, \
2105 .u.periph = { \
2106 .clk_num = _clk_num, \
2107 }, \
2108 }
2109
2110 #define SHARED_CLK(_name, _dev, _con, _parent) \
2111 { \
2112 .name = _name, \
2113 .lookup = { \
2114 .dev_id = _dev, \
2115 .con_id = _con, \
2116 }, \
2117 .ops = &tegra_clk_shared_bus_ops, \
2118 .parent = _parent, \
2119 }
2120
2121 static struct clk tegra_list_clks[] = {
2122 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
2123 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2124 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2125 PERIPH_CLK("i2s1", "tegra-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2126 PERIPH_CLK("i2s2", "tegra-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2127 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2128 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2129 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
2130 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2131 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2132 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2133 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2134 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2135 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2136 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2137 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2138 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2139 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2140 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2141 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2142 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2143 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2144 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2145 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2146 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2147 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2148 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2149 /* FIXME: what is la? */
2150 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2151 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2152 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2153 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2154 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2155 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2156 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2157 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2158 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2159 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2160 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2161 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2162 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2163 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2164 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2165 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2166 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2167 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2168 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2169 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2170 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2171 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2172 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2173 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2174 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2175 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2176 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2177 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2178 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2179 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2180 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2181 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2182 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2183 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2184 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2185 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2186 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2187 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2188 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2189 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2190
2191 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2192 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2193 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2194 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2195 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2196 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2197 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2198 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2199 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2200 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2201 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2202 };
2203
2204 #define CLK_DUPLICATE(_name, _dev, _con) \
2205 { \
2206 .name = _name, \
2207 .lookup = { \
2208 .dev_id = _dev, \
2209 .con_id = _con, \
2210 }, \
2211 }
2212
2213 /* Some clocks may be used by different drivers depending on the board
2214 * configuration. List those here to register them twice in the clock lookup
2215 * table under two names.
2216 */
2217 static struct clk_duplicate tegra_clk_duplicates[] = {
2218 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
2219 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
2220 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
2221 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
2222 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
2223 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2224 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2225 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2226 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2227 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2228 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2229 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2230 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2231 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2232 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2233 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2234 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2235 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2236 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2237 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2238 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2239 };
2240
2241 #define CLK(dev, con, ck) \
2242 { \
2243 .dev_id = dev, \
2244 .con_id = con, \
2245 .clk = ck, \
2246 }
2247
2248 static struct clk *tegra_ptr_clks[] = {
2249 &tegra_clk_32k,
2250 &tegra_pll_s,
2251 &tegra_clk_m,
2252 &tegra_pll_m,
2253 &tegra_pll_m_out1,
2254 &tegra_pll_c,
2255 &tegra_pll_c_out1,
2256 &tegra_pll_p,
2257 &tegra_pll_p_out1,
2258 &tegra_pll_p_out2,
2259 &tegra_pll_p_out3,
2260 &tegra_pll_p_out4,
2261 &tegra_pll_a,
2262 &tegra_pll_a_out0,
2263 &tegra_pll_d,
2264 &tegra_pll_d_out0,
2265 &tegra_pll_u,
2266 &tegra_pll_x,
2267 &tegra_pll_e,
2268 &tegra_clk_cclk,
2269 &tegra_clk_sclk,
2270 &tegra_clk_hclk,
2271 &tegra_clk_pclk,
2272 &tegra_clk_d,
2273 &tegra_clk_cdev1,
2274 &tegra_clk_cdev2,
2275 &tegra_clk_virtual_cpu,
2276 &tegra_clk_blink,
2277 &tegra_clk_cop,
2278 &tegra_clk_emc,
2279 };
2280
2281 static void tegra2_init_one_clock(struct clk *c)
2282 {
2283 clk_init(c);
2284 INIT_LIST_HEAD(&c->shared_bus_list);
2285 if (!c->lookup.dev_id && !c->lookup.con_id)
2286 c->lookup.con_id = c->name;
2287 c->lookup.clk = c;
2288 clkdev_add(&c->lookup);
2289 }
2290
2291 void __init tegra2_init_clocks(void)
2292 {
2293 int i;
2294 struct clk *c;
2295
2296 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2297 tegra2_init_one_clock(tegra_ptr_clks[i]);
2298
2299 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2300 tegra2_init_one_clock(&tegra_list_clks[i]);
2301
2302 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2303 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2304 if (!c) {
2305 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2306 tegra_clk_duplicates[i].name);
2307 continue;
2308 }
2309
2310 tegra_clk_duplicates[i].lookup.clk = c;
2311 clkdev_add(&tegra_clk_duplicates[i].lookup);
2312 }
2313
2314 init_audio_sync_clock_mux();
2315 }
2316
2317 #ifdef CONFIG_PM
2318 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2319 PERIPH_CLK_SOURCE_NUM + 22];
2320
2321 void tegra_clk_suspend(void)
2322 {
2323 unsigned long off, i;
2324 u32 *ctx = clk_rst_suspend;
2325
2326 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2327 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2328 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2329 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2330 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2331 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2332 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2333 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2334 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2335 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2336 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2337
2338 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2339 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2340 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2341
2342 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2343 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2344
2345 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2346 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2347 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2348
2349 *ctx++ = clk_readl(tegra_clk_audio.reg);
2350
2351 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2352 off += 4) {
2353 if (off == PERIPH_CLK_SOURCE_EMC)
2354 continue;
2355 *ctx++ = clk_readl(off);
2356 }
2357
2358 off = RST_DEVICES;
2359 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2360 *ctx++ = clk_readl(off);
2361
2362 off = CLK_OUT_ENB;
2363 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2364 *ctx++ = clk_readl(off);
2365
2366 *ctx++ = clk_readl(MISC_CLK_ENB);
2367 *ctx++ = clk_readl(CLK_MASK_ARM);
2368
2369 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2370 }
2371
2372 void tegra_clk_resume(void)
2373 {
2374 unsigned long off, i;
2375 const u32 *ctx = clk_rst_suspend;
2376 u32 val;
2377
2378 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2379 val |= *ctx++;
2380 clk_writel(val, OSC_CTRL);
2381
2382 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2383 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2384 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2385 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2386 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2387 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2388 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2389 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2390 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2391 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2392 udelay(1000);
2393
2394 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2395 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2396 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2397
2398 clk_writel(*ctx++, tegra_clk_cclk.reg);
2399 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2400
2401 clk_writel(*ctx++, tegra_clk_sclk.reg);
2402 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2403 clk_writel(*ctx++, tegra_clk_pclk.reg);
2404
2405 clk_writel(*ctx++, tegra_clk_audio.reg);
2406
2407 /* enable all clocks before configuring clock sources */
2408 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2409 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2410 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2411 wmb();
2412
2413 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2414 off += 4) {
2415 if (off == PERIPH_CLK_SOURCE_EMC)
2416 continue;
2417 clk_writel(*ctx++, off);
2418 }
2419 wmb();
2420
2421 off = RST_DEVICES;
2422 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2423 clk_writel(*ctx++, off);
2424 wmb();
2425
2426 off = CLK_OUT_ENB;
2427 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2428 clk_writel(*ctx++, off);
2429 wmb();
2430
2431 clk_writel(*ctx++, MISC_CLK_ENB);
2432 clk_writel(*ctx++, CLK_MASK_ARM);
2433 }
2434 #endif