spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / mach-ux500 / headsmp.S
blob08da5589bcd8a60179cc458dba05f735ea6f919f
1 /*
2  *  Copyright (c) 2009 ST-Ericsson
3  *      This file is based  ARM Realview platform
4  *  Copyright (c) 2003 ARM Limited
5  *  All Rights Reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/linkage.h>
12 #include <linux/init.h>
14         __INIT
17  * U8500 specific entry point for secondary CPUs.
18  */
19 ENTRY(u8500_secondary_startup)
20         mrc     p15, 0, r0, c0, c0, 5
21         and     r0, r0, #15
22         adr     r4, 1f
23         ldmia   r4, {r5, r6}
24         sub     r4, r4, r5
25         add     r6, r6, r4
26 pen:    ldr     r7, [r6]
27         cmp     r7, r0
28         bne     pen
30         /*
31          * we've been released from the holding pen: secondary_stack
32          * should now contain the SVC stack for this core
33          */
34         b       secondary_startup
35 ENDPROC(u8500_secondary_startup)
37         .align 2
38 1:      .long   .
39         .long   pen_release