| blob | a655d3da386d6c3620a07bc25176163c21a07e15 |
1 /*
2 * linux/arch/arm/mm/cache-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2005 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This is the "shell" of the ARMv7 processor support.
12 */
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/assembler.h>
16 #include <asm/unwind.h>
18 #include "proc-macros.S"
20 /*
21 * v7_flush_icache_all()
22 *
23 * Flush the whole I-cache.
24 *
25 * Registers:
26 * r0 - set to 0
27 */
28 ENTRY(v7_flush_icache_all)
29 mov r0, #0
30 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
31 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
32 mov pc, lr
33 ENDPROC(v7_flush_icache_all)
35 /*
36 * v7_flush_dcache_all()
37 *
38 * Flush the whole D-cache.
39 *
40 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
41 *
42 * - mm - mm_struct describing address space
43 */
44 ENTRY(v7_flush_dcache_all)
45 dmb @ ensure ordering with previous memory accesses
46 mrc p15, 1, r0, c0, c0, 1 @ read clidr
47 ands r3, r0, #0x7000000 @ extract loc from clidr
48 mov r3, r3, lsr #23 @ left align loc bit field
49 beq finished @ if loc is 0, then no need to clean
50 mov r10, #0 @ start clean at cache level 0
51 loop1:
52 add r2, r10, r10, lsr #1 @ work out 3x current cache level
53 mov r1, r0, lsr r2 @ extract cache type bits from clidr
54 and r1, r1, #7 @ mask of the bits for current cache only
55 cmp r1, #2 @ see what cache we have at this level
56 blt skip @ skip if no cache, or just i-cache
57 #ifdef CONFIG_PREEMPT
58 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
59 #endif
60 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
61 isb @ isb to sych the new cssr&csidr
62 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
63 #ifdef CONFIG_PREEMPT
64 restore_irqs_notrace r9
65 #endif
66 and r2, r1, #7 @ extract the length of the cache lines
67 add r2, r2, #4 @ add 4 (line length offset)
68 ldr r4, =0x3ff
69 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
70 clz r5, r4 @ find bit position of way size increment
71 ldr r7, =0x7fff
72 ands r7, r7, r1, lsr #13 @ extract max number of the index size
73 loop2:
74 mov r9, r4 @ create working copy of max way size
75 loop3:
76 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
77 THUMB( lsl r6, r9, r5 )
78 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
79 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
80 THUMB( lsl r6, r7, r2 )
81 THUMB( orr r11, r11, r6 ) @ factor index number into r11
82 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
83 subs r9, r9, #1 @ decrement the way
84 bge loop3
85 subs r7, r7, #1 @ decrement the index
86 bge loop2
87 skip:
88 add r10, r10, #2 @ increment cache number
89 cmp r3, r10
90 bgt loop1
91 finished:
92 mov r10, #0 @ swith back to cache level 0
93 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
94 dsb
95 isb
96 mov pc, lr
97 ENDPROC(v7_flush_dcache_all)
99 /*
100 * v7_flush_cache_all()
101 *
102 * Flush the entire cache system.
103 * The data cache flush is now achieved using atomic clean / invalidates
104 * working outwards from L1 cache. This is done using Set/Way based cache
105 * maintenance instructions.
106 * The instruction cache can still be invalidated back to the point of
107 * unification in a single instruction.
108 *
109 */
110 ENTRY(v7_flush_kern_cache_all)
111 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
112 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
113 bl v7_flush_dcache_all
114 mov r0, #0
115 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
116 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
117 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
118 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
119 mov pc, lr
120 ENDPROC(v7_flush_kern_cache_all)
122 /*
123 * v7_flush_cache_all()
124 *
125 * Flush all TLB entries in a particular address space
126 *
127 * - mm - mm_struct describing address space
128 */
129 ENTRY(v7_flush_user_cache_all)
130 /*FALLTHROUGH*/
132 /*
133 * v7_flush_cache_range(start, end, flags)
134 *
135 * Flush a range of TLB entries in the specified address space.
136 *
137 * - start - start address (may not be aligned)
138 * - end - end address (exclusive, may not be aligned)
139 * - flags - vm_area_struct flags describing address space
140 *
141 * It is assumed that:
142 * - we have a VIPT cache.
143 */
144 ENTRY(v7_flush_user_cache_range)
145 mov pc, lr
146 ENDPROC(v7_flush_user_cache_all)
147 ENDPROC(v7_flush_user_cache_range)
149 /*
150 * v7_coherent_kern_range(start,end)
151 *
152 * Ensure that the I and D caches are coherent within specified
153 * region. This is typically used when code has been written to
154 * a memory region, and will be executed.
155 *
156 * - start - virtual start address of region
157 * - end - virtual end address of region
158 *
159 * It is assumed that:
160 * - the Icache does not read data from the write buffer
161 */
162 ENTRY(v7_coherent_kern_range)
163 /* FALLTHROUGH */
165 /*
166 * v7_coherent_user_range(start,end)
167 *
168 * Ensure that the I and D caches are coherent within specified
169 * region. This is typically used when code has been written to
170 * a memory region, and will be executed.
171 *
172 * - start - virtual start address of region
173 * - end - virtual end address of region
174 *
175 * It is assumed that:
176 * - the Icache does not read data from the write buffer
177 */
178 ENTRY(v7_coherent_user_range)
179 UNWIND(.fnstart )
180 dcache_line_size r2, r3
181 sub r3, r2, #1
182 bic r12, r0, r3
183 #ifdef CONFIG_ARM_ERRATA_764369
184 ALT_SMP(W(dsb))
185 ALT_UP(W(nop))
186 #endif
187 1:
188 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
189 add r12, r12, r2
190 cmp r12, r1
191 blo 1b
192 dsb
193 icache_line_size r2, r3
194 sub r3, r2, #1
195 bic r12, r0, r3
196 2:
197 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
198 add r12, r12, r2
199 cmp r12, r1
200 blo 2b
201 3:
202 mov r0, #0
203 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
204 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
205 dsb
206 isb
207 mov pc, lr
209 /*
210 * Fault handling for the cache operation above. If the virtual address in r0
211 * isn't mapped, just try the next page.
212 */
213 9001:
214 mov r12, r12, lsr #12
215 mov r12, r12, lsl #12
216 add r12, r12, #4096
217 b 3b
218 UNWIND(.fnend )
219 ENDPROC(v7_coherent_kern_range)
220 ENDPROC(v7_coherent_user_range)
222 /*
223 * v7_flush_kern_dcache_area(void *addr, size_t size)
224 *
225 * Ensure that the data held in the page kaddr is written back
226 * to the page in question.
227 *
228 * - addr - kernel address
229 * - size - region size
230 */
231 ENTRY(v7_flush_kern_dcache_area)
232 dcache_line_size r2, r3
233 add r1, r0, r1
234 sub r3, r2, #1
235 bic r0, r0, r3
236 #ifdef CONFIG_ARM_ERRATA_764369
237 ALT_SMP(W(dsb))
238 ALT_UP(W(nop))
239 #endif
240 1:
241 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
242 add r0, r0, r2
243 cmp r0, r1
244 blo 1b
245 dsb
246 mov pc, lr
247 ENDPROC(v7_flush_kern_dcache_area)
249 /*
250 * v7_dma_inv_range(start,end)
251 *
252 * Invalidate the data cache within the specified region; we will
253 * be performing a DMA operation in this region and we want to
254 * purge old data in the cache.
255 *
256 * - start - virtual start address of region
257 * - end - virtual end address of region
258 */
259 v7_dma_inv_range:
260 dcache_line_size r2, r3
261 sub r3, r2, #1
262 tst r0, r3
263 bic r0, r0, r3
264 #ifdef CONFIG_ARM_ERRATA_764369
265 ALT_SMP(W(dsb))
266 ALT_UP(W(nop))
267 #endif
268 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
270 tst r1, r3
271 bic r1, r1, r3
272 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
273 1:
274 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
275 add r0, r0, r2
276 cmp r0, r1
277 blo 1b
278 dsb
279 mov pc, lr
280 ENDPROC(v7_dma_inv_range)
282 /*
283 * v7_dma_clean_range(start,end)
284 * - start - virtual start address of region
285 * - end - virtual end address of region
286 */
287 v7_dma_clean_range:
288 dcache_line_size r2, r3
289 sub r3, r2, #1
290 bic r0, r0, r3
291 #ifdef CONFIG_ARM_ERRATA_764369
292 ALT_SMP(W(dsb))
293 ALT_UP(W(nop))
294 #endif
295 1:
296 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
297 add r0, r0, r2
298 cmp r0, r1
299 blo 1b
300 dsb
301 mov pc, lr
302 ENDPROC(v7_dma_clean_range)
304 /*
305 * v7_dma_flush_range(start,end)
306 * - start - virtual start address of region
307 * - end - virtual end address of region
308 */
309 ENTRY(v7_dma_flush_range)
310 dcache_line_size r2, r3
311 sub r3, r2, #1
312 bic r0, r0, r3
313 #ifdef CONFIG_ARM_ERRATA_764369
314 ALT_SMP(W(dsb))
315 ALT_UP(W(nop))
316 #endif
317 1:
318 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
319 add r0, r0, r2
320 cmp r0, r1
321 blo 1b
322 dsb
323 mov pc, lr
324 ENDPROC(v7_dma_flush_range)
326 /*
327 * dma_map_area(start, size, dir)
328 * - start - kernel virtual start address
329 * - size - size of region
330 * - dir - DMA direction
331 */
332 ENTRY(v7_dma_map_area)
333 add r1, r1, r0
334 teq r2, #DMA_FROM_DEVICE
335 beq v7_dma_inv_range
336 b v7_dma_clean_range
337 ENDPROC(v7_dma_map_area)
339 /*
340 * dma_unmap_area(start, size, dir)
341 * - start - kernel virtual start address
342 * - size - size of region
343 * - dir - DMA direction
344 */
345 ENTRY(v7_dma_unmap_area)
346 add r1, r1, r0
347 teq r2, #DMA_TO_DEVICE
348 bne v7_dma_inv_range
349 mov pc, lr
350 ENDPROC(v7_dma_unmap_area)
352 __INITDATA
354 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
355 define_cache_functions v7