| blob | 38fe22efd18fc804951b85c22480dd294e4a4790 |
1 /*
2 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 *
14 * These are the low level assembler for performing cache and TLB
15 * functions on the ARM1022E.
16 */
17 #include <linux/linkage.h>
18 #include <linux/init.h>
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/hwcap.h>
22 #include <asm/pgtable-hwdef.h>
23 #include <asm/pgtable.h>
24 #include <asm/ptrace.h>
26 #include "proc-macros.S"
28 /*
29 * This is the maximum size of an area which will be invalidated
30 * using the single invalidate entry instructions. Anything larger
31 * than this, and we go for the whole cache.
32 *
33 * This value should be chosen such that we choose the cheapest
34 * alternative.
35 */
36 #define MAX_AREA_SIZE 32768
38 /*
39 * The size of one data cache line.
40 */
41 #define CACHE_DLINESIZE 32
43 /*
44 * The number of data cache segments.
45 */
46 #define CACHE_DSEGMENTS 16
48 /*
49 * The number of lines in a cache segment.
50 */
51 #define CACHE_DENTRIES 64
53 /*
54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual
56 * cache line maintenance instructions.
57 */
58 #define CACHE_DLIMIT 32768
60 .text
61 /*
62 * cpu_arm1022_proc_init()
63 */
64 ENTRY(cpu_arm1022_proc_init)
65 mov pc, lr
67 /*
68 * cpu_arm1022_proc_fin()
69 */
70 ENTRY(cpu_arm1022_proc_fin)
71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mov pc, lr
77 /*
78 * cpu_arm1022_reset(loc)
79 *
80 * Perform a soft reset of the system. Put the CPU into the
81 * same state as it would be if it had been reset, and branch
82 * to what would be the reset vector.
83 *
84 * loc: location to jump to for soft reset
85 */
86 .align 5
87 .pushsection .idmap.text, "ax"
88 ENTRY(cpu_arm1022_reset)
89 mov ip, #0
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 #ifdef CONFIG_MMU
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 #endif
95 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
96 bic ip, ip, #0x000f @ ............wcam
97 bic ip, ip, #0x1100 @ ...i...s........
98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
99 mov pc, r0
100 ENDPROC(cpu_arm1022_reset)
101 .popsection
103 /*
104 * cpu_arm1022_do_idle()
105 */
106 .align 5
107 ENTRY(cpu_arm1022_do_idle)
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mov pc, lr
111 /* ================================= CACHE ================================ */
113 .align 5
115 /*
116 * flush_icache_all()
117 *
118 * Unconditionally clean and invalidate the entire icache.
119 */
120 ENTRY(arm1022_flush_icache_all)
121 #ifndef CONFIG_CPU_ICACHE_DISABLE
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
124 #endif
125 mov pc, lr
126 ENDPROC(arm1022_flush_icache_all)
128 /*
129 * flush_user_cache_all()
130 *
131 * Invalidate all cache entries in a particular address
132 * space.
133 */
134 ENTRY(arm1022_flush_user_cache_all)
135 /* FALLTHROUGH */
136 /*
137 * flush_kern_cache_all()
138 *
139 * Clean and invalidate the entire cache.
140 */
141 ENTRY(arm1022_flush_kern_cache_all)
142 mov r2, #VM_EXEC
143 mov ip, #0
144 __flush_whole_cache:
145 #ifndef CONFIG_CPU_DCACHE_DISABLE
146 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
147 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 subs r3, r3, #1 << 26
150 bcs 2b @ entries 63 to 0
151 subs r1, r1, #1 << 5
152 bcs 1b @ segments 15 to 0
153 #endif
154 tst r2, #VM_EXEC
155 #ifndef CONFIG_CPU_ICACHE_DISABLE
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 #endif
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 mov pc, lr
161 /*
162 * flush_user_cache_range(start, end, flags)
163 *
164 * Invalidate a range of cache entries in the specified
165 * address space.
166 *
167 * - start - start address (inclusive)
168 * - end - end address (exclusive)
169 * - flags - vm_flags for this space
170 */
171 ENTRY(arm1022_flush_user_cache_range)
172 mov ip, #0
173 sub r3, r1, r0 @ calculate total size
174 cmp r3, #CACHE_DLIMIT
175 bhs __flush_whole_cache
177 #ifndef CONFIG_CPU_DCACHE_DISABLE
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
179 add r0, r0, #CACHE_DLINESIZE
180 cmp r0, r1
181 blo 1b
182 #endif
183 tst r2, #VM_EXEC
184 #ifndef CONFIG_CPU_ICACHE_DISABLE
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 #endif
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 mov pc, lr
190 /*
191 * coherent_kern_range(start, end)
192 *
193 * Ensure coherency between the Icache and the Dcache in the
194 * region described by start. If you have non-snooping
195 * Harvard caches, you need to implement this function.
196 *
197 * - start - virtual start address
198 * - end - virtual end address
199 */
200 ENTRY(arm1022_coherent_kern_range)
201 /* FALLTHROUGH */
203 /*
204 * coherent_user_range(start, end)
205 *
206 * Ensure coherency between the Icache and the Dcache in the
207 * region described by start. If you have non-snooping
208 * Harvard caches, you need to implement this function.
209 *
210 * - start - virtual start address
211 * - end - virtual end address
212 */
213 ENTRY(arm1022_coherent_user_range)
214 mov ip, #0
215 bic r0, r0, #CACHE_DLINESIZE - 1
216 1:
217 #ifndef CONFIG_CPU_DCACHE_DISABLE
218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 #endif
220 #ifndef CONFIG_CPU_ICACHE_DISABLE
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 #endif
223 add r0, r0, #CACHE_DLINESIZE
224 cmp r0, r1
225 blo 1b
226 mcr p15, 0, ip, c7, c10, 4 @ drain WB
227 mov pc, lr
229 /*
230 * flush_kern_dcache_area(void *addr, size_t size)
231 *
232 * Ensure no D cache aliasing occurs, either with itself or
233 * the I cache
234 *
235 * - addr - kernel address
236 * - size - region size
237 */
238 ENTRY(arm1022_flush_kern_dcache_area)
239 mov ip, #0
240 #ifndef CONFIG_CPU_DCACHE_DISABLE
241 add r1, r0, r1
242 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
243 add r0, r0, #CACHE_DLINESIZE
244 cmp r0, r1
245 blo 1b
246 #endif
247 mcr p15, 0, ip, c7, c10, 4 @ drain WB
248 mov pc, lr
250 /*
251 * dma_inv_range(start, end)
252 *
253 * Invalidate (discard) the specified virtual address range.
254 * May not write back any entries. If 'start' or 'end'
255 * are not cache line aligned, those lines must be written
256 * back.
257 *
258 * - start - virtual start address
259 * - end - virtual end address
260 *
261 * (same as v4wb)
262 */
263 arm1022_dma_inv_range:
264 mov ip, #0
265 #ifndef CONFIG_CPU_DCACHE_DISABLE
266 tst r0, #CACHE_DLINESIZE - 1
267 bic r0, r0, #CACHE_DLINESIZE - 1
268 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
269 tst r1, #CACHE_DLINESIZE - 1
270 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
271 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
272 add r0, r0, #CACHE_DLINESIZE
273 cmp r0, r1
274 blo 1b
275 #endif
276 mcr p15, 0, ip, c7, c10, 4 @ drain WB
277 mov pc, lr
279 /*
280 * dma_clean_range(start, end)
281 *
282 * Clean the specified virtual address range.
283 *
284 * - start - virtual start address
285 * - end - virtual end address
286 *
287 * (same as v4wb)
288 */
289 arm1022_dma_clean_range:
290 mov ip, #0
291 #ifndef CONFIG_CPU_DCACHE_DISABLE
292 bic r0, r0, #CACHE_DLINESIZE - 1
293 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
294 add r0, r0, #CACHE_DLINESIZE
295 cmp r0, r1
296 blo 1b
297 #endif
298 mcr p15, 0, ip, c7, c10, 4 @ drain WB
299 mov pc, lr
301 /*
302 * dma_flush_range(start, end)
303 *
304 * Clean and invalidate the specified virtual address range.
305 *
306 * - start - virtual start address
307 * - end - virtual end address
308 */
309 ENTRY(arm1022_dma_flush_range)
310 mov ip, #0
311 #ifndef CONFIG_CPU_DCACHE_DISABLE
312 bic r0, r0, #CACHE_DLINESIZE - 1
313 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
314 add r0, r0, #CACHE_DLINESIZE
315 cmp r0, r1
316 blo 1b
317 #endif
318 mcr p15, 0, ip, c7, c10, 4 @ drain WB
319 mov pc, lr
321 /*
322 * dma_map_area(start, size, dir)
323 * - start - kernel virtual start address
324 * - size - size of region
325 * - dir - DMA direction
326 */
327 ENTRY(arm1022_dma_map_area)
328 add r1, r1, r0
329 cmp r2, #DMA_TO_DEVICE
330 beq arm1022_dma_clean_range
331 bcs arm1022_dma_inv_range
332 b arm1022_dma_flush_range
333 ENDPROC(arm1022_dma_map_area)
335 /*
336 * dma_unmap_area(start, size, dir)
337 * - start - kernel virtual start address
338 * - size - size of region
339 * - dir - DMA direction
340 */
341 ENTRY(arm1022_dma_unmap_area)
342 mov pc, lr
343 ENDPROC(arm1022_dma_unmap_area)
345 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
346 define_cache_functions arm1022
348 .align 5
349 ENTRY(cpu_arm1022_dcache_clean_area)
350 #ifndef CONFIG_CPU_DCACHE_DISABLE
351 mov ip, #0
352 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 add r0, r0, #CACHE_DLINESIZE
354 subs r1, r1, #CACHE_DLINESIZE
355 bhi 1b
356 #endif
357 mov pc, lr
359 /* =============================== PageTable ============================== */
361 /*
362 * cpu_arm1022_switch_mm(pgd)
363 *
364 * Set the translation base pointer to be as described by pgd.
365 *
366 * pgd: new page tables
367 */
368 .align 5
369 ENTRY(cpu_arm1022_switch_mm)
370 #ifdef CONFIG_MMU
371 #ifndef CONFIG_CPU_DCACHE_DISABLE
372 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
373 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
374 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
375 subs r3, r3, #1 << 26
376 bcs 2b @ entries 63 to 0
377 subs r1, r1, #1 << 5
378 bcs 1b @ segments 15 to 0
379 #endif
380 mov r1, #0
381 #ifndef CONFIG_CPU_ICACHE_DISABLE
382 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
383 #endif
384 mcr p15, 0, r1, c7, c10, 4 @ drain WB
385 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
386 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
387 #endif
388 mov pc, lr
390 /*
391 * cpu_arm1022_set_pte_ext(ptep, pte, ext)
392 *
393 * Set a PTE and flush it out
394 */
395 .align 5
396 ENTRY(cpu_arm1022_set_pte_ext)
397 #ifdef CONFIG_MMU
398 armv3_set_pte_ext
399 mov r0, r0
400 #ifndef CONFIG_CPU_DCACHE_DISABLE
401 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
402 #endif
403 #endif /* CONFIG_MMU */
404 mov pc, lr
406 __CPUINIT
408 .type __arm1022_setup, #function
409 __arm1022_setup:
410 mov r0, #0
411 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
412 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
413 #ifdef CONFIG_MMU
414 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
415 #endif
416 adr r5, arm1022_crval
417 ldmia r5, {r5, r6}
418 mrc p15, 0, r0, c1, c0 @ get control register v4
419 bic r0, r0, r5
420 orr r0, r0, r6
421 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
422 orr r0, r0, #0x4000 @ .R..............
423 #endif
424 mov pc, lr
425 .size __arm1022_setup, . - __arm1022_setup
427 /*
428 * R
429 * .RVI ZFRS BLDP WCAM
430 * .011 1001 ..11 0101
431 *
432 */
433 .type arm1022_crval, #object
434 arm1022_crval:
435 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
437 __INITDATA
438 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
439 define_processor_functions arm1022, dabort=v4t_early_abort, pabort=legacy_pabort
441 .section ".rodata"
443 string cpu_arch_name, "armv5te"
444 string cpu_elf_name, "v5"
445 string cpu_arm1022_name, "ARM1022"
447 .align
449 .section ".proc.info.init", #alloc, #execinstr
451 .type __arm1022_proc_info,#object
452 __arm1022_proc_info:
453 .long 0x4105a220 @ ARM 1022E (v5TE)
454 .long 0xff0ffff0
455 .long PMD_TYPE_SECT | \
456 PMD_BIT4 | \
457 PMD_SECT_AP_WRITE | \
458 PMD_SECT_AP_READ
459 .long PMD_TYPE_SECT | \
460 PMD_BIT4 | \
461 PMD_SECT_AP_WRITE | \
462 PMD_SECT_AP_READ
463 b __arm1022_setup
464 .long cpu_arch_name
465 .long cpu_elf_name
466 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
467 .long cpu_arm1022_name
468 .long arm1022_processor_functions
469 .long v4wbi_tlb_fns
470 .long v4wb_user_fns
471 .long arm1022_cache_fns
472 .size __arm1022_proc_info, . - __arm1022_proc_info