| blob | 2b7c08d13e89be022848ced8f176a9760d0ce86d |
1 /*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
12 #ifndef __MACH_MX1_H__
13 #define __MACH_MX1_H__
15 /*
16 * Memory map
17 */
18 #define MX1_IO_BASE_ADDR 0x00200000
19 #define MX1_IO_SIZE SZ_1M
21 #define MX1_CS0_PHYS 0x10000000
22 #define MX1_CS0_SIZE 0x02000000
24 #define MX1_CS1_PHYS 0x12000000
25 #define MX1_CS1_SIZE 0x01000000
27 #define MX1_CS2_PHYS 0x13000000
28 #define MX1_CS2_SIZE 0x01000000
30 #define MX1_CS3_PHYS 0x14000000
31 #define MX1_CS3_SIZE 0x01000000
33 #define MX1_CS4_PHYS 0x15000000
34 #define MX1_CS4_SIZE 0x01000000
36 #define MX1_CS5_PHYS 0x16000000
37 #define MX1_CS5_SIZE 0x01000000
39 /*
40 * Register BASEs, based on OFFSETs
41 */
42 #define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
43 #define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
44 #define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
45 #define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
46 #define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
47 #define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
48 #define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
49 #define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
50 #define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
51 #define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
52 #define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
53 #define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
54 #define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
55 #define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
56 #define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
57 #define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
58 #define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
59 #define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
60 #define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
61 #define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
62 #define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
63 #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
64 #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
65 #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
66 #define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
67 #define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
68 #define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
69 #define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
70 #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
71 #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
72 #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
73 #define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
74 #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
76 /* macro to get at IO space when running virtually */
77 #define MX1_IO_P2V(x) IMX_IO_P2V(x)
78 #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
80 /* fixed interrput numbers */
81 #define MX1_INT_SOFTINT 0
82 #define MX1_INT_CSI 6
83 #define MX1_DSPA_MAC_INT 7
84 #define MX1_DSPA_INT 8
85 #define MX1_COMP_INT 9
86 #define MX1_MSHC_XINT 10
87 #define MX1_GPIO_INT_PORTA 11
88 #define MX1_GPIO_INT_PORTB 12
89 #define MX1_GPIO_INT_PORTC 13
90 #define MX1_INT_LCDC 14
91 #define MX1_SIM_INT 15
92 #define MX1_SIM_DATA_INT 16
93 #define MX1_RTC_INT 17
94 #define MX1_RTC_SAMINT 18
95 #define MX1_INT_UART2PFERR 19
96 #define MX1_INT_UART2RTS 20
97 #define MX1_INT_UART2DTR 21
98 #define MX1_INT_UART2UARTC 22
99 #define MX1_INT_UART2TX 23
100 #define MX1_INT_UART2RX 24
101 #define MX1_INT_UART1PFERR 25
102 #define MX1_INT_UART1RTS 26
103 #define MX1_INT_UART1DTR 27
104 #define MX1_INT_UART1UARTC 28
105 #define MX1_INT_UART1TX 29
106 #define MX1_INT_UART1RX 30
107 #define MX1_VOICE_DAC_INT 31
108 #define MX1_VOICE_ADC_INT 32
109 #define MX1_PEN_DATA_INT 33
110 #define MX1_PWM_INT 34
111 #define MX1_SDHC_INT 35
112 #define MX1_INT_I2C 39
113 #define MX1_INT_CSPI2 40
114 #define MX1_INT_CSPI1 41
115 #define MX1_SSI_TX_INT 42
116 #define MX1_SSI_TX_ERR_INT 43
117 #define MX1_SSI_RX_INT 44
118 #define MX1_SSI_RX_ERR_INT 45
119 #define MX1_TOUCH_INT 46
120 #define MX1_INT_USBD0 47
121 #define MX1_INT_USBD1 48
122 #define MX1_INT_USBD2 49
123 #define MX1_INT_USBD3 50
124 #define MX1_INT_USBD4 51
125 #define MX1_INT_USBD5 52
126 #define MX1_INT_USBD6 53
127 #define MX1_BTSYS_INT 55
128 #define MX1_BTTIM_INT 56
129 #define MX1_BTWUI_INT 57
130 #define MX1_TIM2_INT 58
131 #define MX1_TIM1_INT 59
132 #define MX1_DMA_ERR 60
133 #define MX1_DMA_INT 61
134 #define MX1_GPIO_INT_PORTD 62
135 #define MX1_WDT_INT 63
137 /* DMA */
138 #define MX1_DMA_REQ_UART3_T 2
139 #define MX1_DMA_REQ_UART3_R 3
140 #define MX1_DMA_REQ_SSI2_T 4
141 #define MX1_DMA_REQ_SSI2_R 5
142 #define MX1_DMA_REQ_CSI_STAT 6
143 #define MX1_DMA_REQ_CSI_R 7
144 #define MX1_DMA_REQ_MSHC 8
145 #define MX1_DMA_REQ_DSPA_DCT_DOUT 9
146 #define MX1_DMA_REQ_DSPA_DCT_DIN 10
147 #define MX1_DMA_REQ_DSPA_MAC 11
148 #define MX1_DMA_REQ_EXT 12
149 #define MX1_DMA_REQ_SDHC 13
150 #define MX1_DMA_REQ_SPI1_R 14
151 #define MX1_DMA_REQ_SPI1_T 15
152 #define MX1_DMA_REQ_SSI_T 16
153 #define MX1_DMA_REQ_SSI_R 17
154 #define MX1_DMA_REQ_ASP_DAC 18
155 #define MX1_DMA_REQ_ASP_ADC 19
156 #define MX1_DMA_REQ_USP_EP(x) (20 + (x))
157 #define MX1_DMA_REQ_SPI2_R 26
158 #define MX1_DMA_REQ_SPI2_T 27
159 #define MX1_DMA_REQ_UART2_T 28
160 #define MX1_DMA_REQ_UART2_R 29
161 #define MX1_DMA_REQ_UART1_T 30
162 #define MX1_DMA_REQ_UART1_R 31
164 /*
165 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
166 * to not break drivers/usb/gadget/imx_udc. Should go
167 * away after this driver uses the new name.
168 */
169 #define USBD_INT0 MX1_INT_USBD0