arch/arm/plat-nomadik/timer.c

   1 /*
   2  *  linux/arch/arm/plat-nomadik/timer.c
   3  *
   4  * Copyright (C) 2008 STMicroelectronics
   5  * Copyright (C) 2010 Alessandro Rubini
   6  * Copyright (C) 2010 Linus Walleij for ST-Ericsson
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2, as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/clk.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/err.h>
  20 #include <asm/mach/time.h>
  21 #include <asm/sched_clock.h>
  22
  23 /*
  24  * Guaranteed runtime conversion range in seconds for
  25  * the clocksource and clockevent.
  26  */
  27 #define MTU_MIN_RANGE 4
  28
  29 /*
  30  * The MTU device hosts four different counters, with 4 set of
  31  * registers. These are register names.
  32  */
  33
  34 #define MTU_IMSC        0x00    /* Interrupt mask set/clear */
  35 #define MTU_RIS         0x04    /* Raw interrupt status */
  36 #define MTU_MIS         0x08    /* Masked interrupt status */
  37 #define MTU_ICR         0x0C    /* Interrupt clear register */
  38
  39 /* per-timer registers take 0..3 as argument */
  40 #define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
  41 #define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
  42 #define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
  43 #define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
  44
  45 /* bits for the control register */
  46 #define MTU_CRn_ENA             0x80
  47 #define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
  48 #define MTU_CRn_PRESCALE_MASK   0x0c
  49 #define MTU_CRn_PRESCALE_1              0x00
  50 #define MTU_CRn_PRESCALE_16             0x04
  51 #define MTU_CRn_PRESCALE_256            0x08
  52 #define MTU_CRn_32BITS          0x02
  53 #define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
  54
  55 /* Other registers are usual amba/primecell registers, currently not used */
  56 #define MTU_ITCR        0xff0
  57 #define MTU_ITOP        0xff4
  58
  59 #define MTU_PERIPH_ID0  0xfe0
  60 #define MTU_PERIPH_ID1  0xfe4
  61 #define MTU_PERIPH_ID2  0xfe8
  62 #define MTU_PERIPH_ID3  0xfeC
  63
  64 #define MTU_PCELL0      0xff0
  65 #define MTU_PCELL1      0xff4
  66 #define MTU_PCELL2      0xff8
  67 #define MTU_PCELL3      0xffC
  68
  69 static bool clkevt_periodic;
  70 static u32 clk_prescale;
  71 static u32 nmdk_cycle;          /* write-once */
  72
  73 void __iomem *mtu_base; /* Assigned by machine code */
  74
  75 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
  76 /*
  77  * Override the global weak sched_clock symbol with this
  78  * local implementation which uses the clocksource to get some
  79  * better resolution when scheduling the kernel.
  80  */
  81 static u32 notrace nomadik_read_sched_clock(void)
  82 {
  83         if (unlikely(!mtu_base))
  84                 return 0;
  85
  86         return -readl(mtu_base + MTU_VAL(0));
  87 }
  88 #endif
  89
  90 /* Clockevent device: use one-shot mode */
  91 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
  92 {
  93         writel(1 << 1, mtu_base + MTU_IMSC);
  94         writel(evt, mtu_base + MTU_LR(1));
  95         /* Load highest value, enable device, enable interrupts */
  96         writel(MTU_CRn_ONESHOT | clk_prescale |
  97                MTU_CRn_32BITS | MTU_CRn_ENA,
  98                mtu_base + MTU_CR(1));
  99
 100         return 0;
 101 }
 102
 103 void nmdk_clkevt_reset(void)
 104 {
 105         if (clkevt_periodic) {
 106
 107                 /* Timer: configure load and background-load, and fire it up */
 108                 writel(nmdk_cycle, mtu_base + MTU_LR(1));
 109                 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
 110
 111                 writel(MTU_CRn_PERIODIC | clk_prescale |
 112                        MTU_CRn_32BITS | MTU_CRn_ENA,
 113                        mtu_base + MTU_CR(1));
 114                 writel(1 << 1, mtu_base + MTU_IMSC);
 115         } else {
 116                 /* Generate an interrupt to start the clockevent again */
 117                 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
 118         }
 119 }
 120
 121 static void nmdk_clkevt_mode(enum clock_event_mode mode,
 122                              struct clock_event_device *dev)
 123 {
 124
 125         switch (mode) {
 126         case CLOCK_EVT_MODE_PERIODIC:
 127                 clkevt_periodic = true;
 128                 nmdk_clkevt_reset();
 129                 break;
 130         case CLOCK_EVT_MODE_ONESHOT:
 131                 clkevt_periodic = false;
 132                 break;
 133         case CLOCK_EVT_MODE_SHUTDOWN:
 134         case CLOCK_EVT_MODE_UNUSED:
 135                 writel(0, mtu_base + MTU_IMSC);
 136                 /* disable timer */
 137                 writel(0, mtu_base + MTU_CR(1));
 138                 /* load some high default value */
 139                 writel(0xffffffff, mtu_base + MTU_LR(1));
 140                 break;
 141         case CLOCK_EVT_MODE_RESUME:
 142                 break;
 143         }
 144 }
 145
 146 static struct clock_event_device nmdk_clkevt = {
 147         .name           = "mtu_1",
 148         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 149         .rating         = 200,
 150         .set_mode       = nmdk_clkevt_mode,
 151         .set_next_event = nmdk_clkevt_next,
 152 };
 153
 154 /*
 155  * IRQ Handler for timer 1 of the MTU block.
 156  */
 157 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 158 {
 159         struct clock_event_device *evdev = dev_id;
 160
 161         writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
 162         evdev->event_handler(evdev);
 163         return IRQ_HANDLED;
 164 }
 165
 166 static struct irqaction nmdk_timer_irq = {
 167         .name           = "Nomadik Timer Tick",
 168         .flags          = IRQF_DISABLED | IRQF_TIMER,
 169         .handler        = nmdk_timer_interrupt,
 170         .dev_id         = &nmdk_clkevt,
 171 };
 172
 173 void nmdk_clksrc_reset(void)
 174 {
 175         /* Disable */
 176         writel(0, mtu_base + MTU_CR(0));
 177
 178         /* ClockSource: configure load and background-load, and fire it up */
 179         writel(nmdk_cycle, mtu_base + MTU_LR(0));
 180         writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
 181
 182         writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
 183                mtu_base + MTU_CR(0));
 184 }
 185
 186 void __init nmdk_timer_init(void)
 187 {
 188         unsigned long rate;
 189         struct clk *clk0;
 190
 191         clk0 = clk_get_sys("mtu0", NULL);
 192         BUG_ON(IS_ERR(clk0));
 193
 194         clk_enable(clk0);
 195
 196         /*
 197          * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
 198          * for ux500.
 199          * Use a divide-by-16 counter if the tick rate is more than 32MHz.
 200          * At 32 MHz, the timer (with 32 bit counter) can be programmed
 201          * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
 202          * with 16 gives too low timer resolution.
 203          */
 204         rate = clk_get_rate(clk0);
 205         if (rate > 32000000) {
 206                 rate /= 16;
 207                 clk_prescale = MTU_CRn_PRESCALE_16;
 208         } else {
 209                 clk_prescale = MTU_CRn_PRESCALE_1;
 210         }
 211
 212         nmdk_cycle = (rate + HZ/2) / HZ;
 213
 214
 215         /* Timer 0 is the free running clocksource */
 216         nmdk_clksrc_reset();
 217
 218         if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
 219                         rate, 200, 32, clocksource_mmio_readl_down))
 220                 pr_err("timer: failed to initialize clock source %s\n",
 221                        "mtu_0");
 222
 223 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
 224         setup_sched_clock(nomadik_read_sched_clock, 32, rate);
 225 #endif
 226
 227         /* Timer 1 is used for events */
 228
 229         clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
 230
 231         nmdk_clkevt.max_delta_ns =
 232                 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
 233         nmdk_clkevt.min_delta_ns =
 234                 clockevent_delta2ns(0x00000002, &nmdk_clkevt);
 235         nmdk_clkevt.cpumask     = cpumask_of(0);
 236
 237         /* Register irq and clockevents */
 238         setup_irq(IRQ_MTU0, &nmdk_timer_irq);
 239         clockevents_register_device(&nmdk_clkevt);
 240 }