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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / plat-omap / dma.c
blob002fb4d96bbc7020b6158b469040faf29c72b891
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Support functions for the OMAP internal DMA channels.
17 *
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 *
26 */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <asm/system.h>
40 #include <mach/hardware.h>
41 #include <plat/dma.h>
42
43 #include <plat/tc.h>
44
45 #undef DEBUG
46
47 #ifndef CONFIG_ARCH_OMAP1
48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
49 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
50 };
51
52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
53 #endif
54
55 #define OMAP_DMA_ACTIVE 0x01
56 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
57
58 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
59
60 static struct omap_system_dma_plat_info *p;
61 static struct omap_dma_dev_attr *d;
62
63 static int enable_1510_mode;
64 static u32 errata;
65
66 static struct omap_dma_global_context_registers {
67 u32 dma_irqenable_l0;
68 u32 dma_ocp_sysconfig;
69 u32 dma_gcr;
70 } omap_dma_global_context;
71
72 struct dma_link_info {
73 int *linked_dmach_q;
74 int no_of_lchs_linked;
75
76 int q_count;
77 int q_tail;
78 int q_head;
79
80 int chain_state;
81 int chain_mode;
82
83 };
84
85 static struct dma_link_info *dma_linked_lch;
86
87 #ifndef CONFIG_ARCH_OMAP1
88
89 /* Chain handling macros */
90 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
91 do { \
92 dma_linked_lch[chain_id].q_head = \
93 dma_linked_lch[chain_id].q_tail = \
94 dma_linked_lch[chain_id].q_count = 0; \
95 } while (0)
96 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
97 (dma_linked_lch[chain_id].no_of_lchs_linked == \
98 dma_linked_lch[chain_id].q_count)
99 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
100 do { \
101 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
102 dma_linked_lch[chain_id].q_count) \
103 } while (0)
104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
105 (0 == dma_linked_lch[chain_id].q_count)
106 #define __OMAP_DMA_CHAIN_INCQ(end) \
107 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
109 do { \
110 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
111 dma_linked_lch[chain_id].q_count--; \
112 } while (0)
113
114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
115 do { \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
117 dma_linked_lch[chain_id].q_count++; \
118 } while (0)
119 #endif
120
121 static int dma_lch_count;
122 static int dma_chan_count;
123 static int omap_dma_reserve_channels;
124
125 static spinlock_t dma_chan_lock;
126 static struct omap_dma_lch *dma_chan;
127
128 static inline void disable_lnk(int lch);
129 static void omap_disable_channel_irq(int lch);
130 static inline void omap_enable_channel_irq(int lch);
131
132 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
133 __func__);
134
135 #ifdef CONFIG_ARCH_OMAP15XX
136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
137 static int omap_dma_in_1510_mode(void)
138 {
139 return enable_1510_mode;
140 }
141 #else
142 #define omap_dma_in_1510_mode() 0
143 #endif
144
145 #ifdef CONFIG_ARCH_OMAP1
146 static inline int get_gdma_dev(int req)
147 {
148 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
149 int shift = ((req - 1) % 5) * 6;
150
151 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
152 }
153
154 static inline void set_gdma_dev(int req, int dev)
155 {
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
158 u32 l;
159
160 l = omap_readl(reg);
161 l &= ~(0x3f << shift);
162 l |= (dev - 1) << shift;
163 omap_writel(l, reg);
164 }
165 #else
166 #define set_gdma_dev(req, dev) do {} while (0)
167 #endif
168
169 void omap_set_dma_priority(int lch, int dst_port, int priority)
170 {
171 unsigned long reg;
172 u32 l;
173
174 if (cpu_class_is_omap1()) {
175 switch (dst_port) {
176 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
177 reg = OMAP_TC_OCPT1_PRIOR;
178 break;
179 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
180 reg = OMAP_TC_OCPT2_PRIOR;
181 break;
182 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
183 reg = OMAP_TC_EMIFF_PRIOR;
184 break;
185 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
186 reg = OMAP_TC_EMIFS_PRIOR;
187 break;
188 default:
189 BUG();
190 return;
191 }
192 l = omap_readl(reg);
193 l &= ~(0xf << 8);
194 l |= (priority & 0xf) << 8;
195 omap_writel(l, reg);
196 }
197
198 if (cpu_class_is_omap2()) {
199 u32 ccr;
200
201 ccr = p->dma_read(CCR, lch);
202 if (priority)
203 ccr |= (1 << 6);
204 else
205 ccr &= ~(1 << 6);
206 p->dma_write(ccr, CCR, lch);
207 }
208 }
209 EXPORT_SYMBOL(omap_set_dma_priority);
210
211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
212 int frame_count, int sync_mode,
213 int dma_trigger, int src_or_dst_synch)
214 {
215 u32 l;
216
217 l = p->dma_read(CSDP, lch);
218 l &= ~0x03;
219 l |= data_type;
220 p->dma_write(l, CSDP, lch);
221
222 if (cpu_class_is_omap1()) {
223 u16 ccr;
224
225 ccr = p->dma_read(CCR, lch);
226 ccr &= ~(1 << 5);
227 if (sync_mode == OMAP_DMA_SYNC_FRAME)
228 ccr |= 1 << 5;
229 p->dma_write(ccr, CCR, lch);
230
231 ccr = p->dma_read(CCR2, lch);
232 ccr &= ~(1 << 2);
233 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
234 ccr |= 1 << 2;
235 p->dma_write(ccr, CCR2, lch);
236 }
237
238 if (cpu_class_is_omap2() && dma_trigger) {
239 u32 val;
240
241 val = p->dma_read(CCR, lch);
242
243 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
244 val &= ~((1 << 23) | (3 << 19) | 0x1f);
245 val |= (dma_trigger & ~0x1f) << 14;
246 val |= dma_trigger & 0x1f;
247
248 if (sync_mode & OMAP_DMA_SYNC_FRAME)
249 val |= 1 << 5;
250 else
251 val &= ~(1 << 5);
252
253 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
254 val |= 1 << 18;
255 else
256 val &= ~(1 << 18);
257
258 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
259 val &= ~(1 << 24); /* dest synch */
260 val |= (1 << 23); /* Prefetch */
261 } else if (src_or_dst_synch) {
262 val |= 1 << 24; /* source synch */
263 } else {
264 val &= ~(1 << 24); /* dest synch */
265 }
266 p->dma_write(val, CCR, lch);
267 }
268
269 p->dma_write(elem_count, CEN, lch);
270 p->dma_write(frame_count, CFN, lch);
271 }
272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
273
274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
275 {
276 BUG_ON(omap_dma_in_1510_mode());
277
278 if (cpu_class_is_omap1()) {
279 u16 w;
280
281 w = p->dma_read(CCR2, lch);
282 w &= ~0x03;
283
284 switch (mode) {
285 case OMAP_DMA_CONSTANT_FILL:
286 w |= 0x01;
287 break;
288 case OMAP_DMA_TRANSPARENT_COPY:
289 w |= 0x02;
290 break;
291 case OMAP_DMA_COLOR_DIS:
292 break;
293 default:
294 BUG();
295 }
296 p->dma_write(w, CCR2, lch);
297
298 w = p->dma_read(LCH_CTRL, lch);
299 w &= ~0x0f;
300 /* Default is channel type 2D */
301 if (mode) {
302 p->dma_write(color, COLOR, lch);
303 w |= 1; /* Channel type G */
304 }
305 p->dma_write(w, LCH_CTRL, lch);
306 }
307
308 if (cpu_class_is_omap2()) {
309 u32 val;
310
311 val = p->dma_read(CCR, lch);
312 val &= ~((1 << 17) | (1 << 16));
313
314 switch (mode) {
315 case OMAP_DMA_CONSTANT_FILL:
316 val |= 1 << 16;
317 break;
318 case OMAP_DMA_TRANSPARENT_COPY:
319 val |= 1 << 17;
320 break;
321 case OMAP_DMA_COLOR_DIS:
322 break;
323 default:
324 BUG();
325 }
326 p->dma_write(val, CCR, lch);
327
328 color &= 0xffffff;
329 p->dma_write(color, COLOR, lch);
330 }
331 }
332 EXPORT_SYMBOL(omap_set_dma_color_mode);
333
334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
335 {
336 if (cpu_class_is_omap2()) {
337 u32 csdp;
338
339 csdp = p->dma_read(CSDP, lch);
340 csdp &= ~(0x3 << 16);
341 csdp |= (mode << 16);
342 p->dma_write(csdp, CSDP, lch);
343 }
344 }
345 EXPORT_SYMBOL(omap_set_dma_write_mode);
346
347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
348 {
349 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
350 u32 l;
351
352 l = p->dma_read(LCH_CTRL, lch);
353 l &= ~0x7;
354 l |= mode;
355 p->dma_write(l, LCH_CTRL, lch);
356 }
357 }
358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
359
360 /* Note that src_port is only for omap1 */
361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
362 unsigned long src_start,
363 int src_ei, int src_fi)
364 {
365 u32 l;
366
367 if (cpu_class_is_omap1()) {
368 u16 w;
369
370 w = p->dma_read(CSDP, lch);
371 w &= ~(0x1f << 2);
372 w |= src_port << 2;
373 p->dma_write(w, CSDP, lch);
374 }
375
376 l = p->dma_read(CCR, lch);
377 l &= ~(0x03 << 12);
378 l |= src_amode << 12;
379 p->dma_write(l, CCR, lch);
380
381 p->dma_write(src_start, CSSA, lch);
382
383 p->dma_write(src_ei, CSEI, lch);
384 p->dma_write(src_fi, CSFI, lch);
385 }
386 EXPORT_SYMBOL(omap_set_dma_src_params);
387
388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
389 {
390 omap_set_dma_transfer_params(lch, params->data_type,
391 params->elem_count, params->frame_count,
392 params->sync_mode, params->trigger,
393 params->src_or_dst_synch);
394 omap_set_dma_src_params(lch, params->src_port,
395 params->src_amode, params->src_start,
396 params->src_ei, params->src_fi);
397
398 omap_set_dma_dest_params(lch, params->dst_port,
399 params->dst_amode, params->dst_start,
400 params->dst_ei, params->dst_fi);
401 if (params->read_prio || params->write_prio)
402 omap_dma_set_prio_lch(lch, params->read_prio,
403 params->write_prio);
404 }
405 EXPORT_SYMBOL(omap_set_dma_params);
406
407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
408 {
409 if (cpu_class_is_omap2())
410 return;
411
412 p->dma_write(eidx, CSEI, lch);
413 p->dma_write(fidx, CSFI, lch);
414 }
415 EXPORT_SYMBOL(omap_set_dma_src_index);
416
417 void omap_set_dma_src_data_pack(int lch, int enable)
418 {
419 u32 l;
420
421 l = p->dma_read(CSDP, lch);
422 l &= ~(1 << 6);
423 if (enable)
424 l |= (1 << 6);
425 p->dma_write(l, CSDP, lch);
426 }
427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
428
429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
430 {
431 unsigned int burst = 0;
432 u32 l;
433
434 l = p->dma_read(CSDP, lch);
435 l &= ~(0x03 << 7);
436
437 switch (burst_mode) {
438 case OMAP_DMA_DATA_BURST_DIS:
439 break;
440 case OMAP_DMA_DATA_BURST_4:
441 if (cpu_class_is_omap2())
442 burst = 0x1;
443 else
444 burst = 0x2;
445 break;
446 case OMAP_DMA_DATA_BURST_8:
447 if (cpu_class_is_omap2()) {
448 burst = 0x2;
449 break;
450 }
451 /*
452 * not supported by current hardware on OMAP1
453 * w |= (0x03 << 7);
454 * fall through
455 */
456 case OMAP_DMA_DATA_BURST_16:
457 if (cpu_class_is_omap2()) {
458 burst = 0x3;
459 break;
460 }
461 /*
462 * OMAP1 don't support burst 16
463 * fall through
464 */
465 default:
466 BUG();
467 }
468
469 l |= (burst << 7);
470 p->dma_write(l, CSDP, lch);
471 }
472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
473
474 /* Note that dest_port is only for OMAP1 */
475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
476 unsigned long dest_start,
477 int dst_ei, int dst_fi)
478 {
479 u32 l;
480
481 if (cpu_class_is_omap1()) {
482 l = p->dma_read(CSDP, lch);
483 l &= ~(0x1f << 9);
484 l |= dest_port << 9;
485 p->dma_write(l, CSDP, lch);
486 }
487
488 l = p->dma_read(CCR, lch);
489 l &= ~(0x03 << 14);
490 l |= dest_amode << 14;
491 p->dma_write(l, CCR, lch);
492
493 p->dma_write(dest_start, CDSA, lch);
494
495 p->dma_write(dst_ei, CDEI, lch);
496 p->dma_write(dst_fi, CDFI, lch);
497 }
498 EXPORT_SYMBOL(omap_set_dma_dest_params);
499
500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
501 {
502 if (cpu_class_is_omap2())
503 return;
504
505 p->dma_write(eidx, CDEI, lch);
506 p->dma_write(fidx, CDFI, lch);
507 }
508 EXPORT_SYMBOL(omap_set_dma_dest_index);
509
510 void omap_set_dma_dest_data_pack(int lch, int enable)
511 {
512 u32 l;
513
514 l = p->dma_read(CSDP, lch);
515 l &= ~(1 << 13);
516 if (enable)
517 l |= 1 << 13;
518 p->dma_write(l, CSDP, lch);
519 }
520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
521
522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
523 {
524 unsigned int burst = 0;
525 u32 l;
526
527 l = p->dma_read(CSDP, lch);
528 l &= ~(0x03 << 14);
529
530 switch (burst_mode) {
531 case OMAP_DMA_DATA_BURST_DIS:
532 break;
533 case OMAP_DMA_DATA_BURST_4:
534 if (cpu_class_is_omap2())
535 burst = 0x1;
536 else
537 burst = 0x2;
538 break;
539 case OMAP_DMA_DATA_BURST_8:
540 if (cpu_class_is_omap2())
541 burst = 0x2;
542 else
543 burst = 0x3;
544 break;
545 case OMAP_DMA_DATA_BURST_16:
546 if (cpu_class_is_omap2()) {
547 burst = 0x3;
548 break;
549 }
550 /*
551 * OMAP1 don't support burst 16
552 * fall through
553 */
554 default:
555 printk(KERN_ERR "Invalid DMA burst mode\n");
556 BUG();
557 return;
558 }
559 l |= (burst << 14);
560 p->dma_write(l, CSDP, lch);
561 }
562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
563
564 static inline void omap_enable_channel_irq(int lch)
565 {
566 u32 status;
567
568 /* Clear CSR */
569 if (cpu_class_is_omap1())
570 status = p->dma_read(CSR, lch);
571 else if (cpu_class_is_omap2())
572 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
573
574 /* Enable some nice interrupts. */
575 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
576 }
577
578 static void omap_disable_channel_irq(int lch)
579 {
580 if (cpu_class_is_omap2())
581 p->dma_write(0, CICR, lch);
582 }
583
584 void omap_enable_dma_irq(int lch, u16 bits)
585 {
586 dma_chan[lch].enabled_irqs |= bits;
587 }
588 EXPORT_SYMBOL(omap_enable_dma_irq);
589
590 void omap_disable_dma_irq(int lch, u16 bits)
591 {
592 dma_chan[lch].enabled_irqs &= ~bits;
593 }
594 EXPORT_SYMBOL(omap_disable_dma_irq);
595
596 static inline void enable_lnk(int lch)
597 {
598 u32 l;
599
600 l = p->dma_read(CLNK_CTRL, lch);
601
602 if (cpu_class_is_omap1())
603 l &= ~(1 << 14);
604
605 /* Set the ENABLE_LNK bits */
606 if (dma_chan[lch].next_lch != -1)
607 l = dma_chan[lch].next_lch | (1 << 15);
608
609 #ifndef CONFIG_ARCH_OMAP1
610 if (cpu_class_is_omap2())
611 if (dma_chan[lch].next_linked_ch != -1)
612 l = dma_chan[lch].next_linked_ch | (1 << 15);
613 #endif
614
615 p->dma_write(l, CLNK_CTRL, lch);
616 }
617
618 static inline void disable_lnk(int lch)
619 {
620 u32 l;
621
622 l = p->dma_read(CLNK_CTRL, lch);
623
624 /* Disable interrupts */
625 if (cpu_class_is_omap1()) {
626 p->dma_write(0, CICR, lch);
627 /* Set the STOP_LNK bit */
628 l |= 1 << 14;
629 }
630
631 if (cpu_class_is_omap2()) {
632 omap_disable_channel_irq(lch);
633 /* Clear the ENABLE_LNK bit */
634 l &= ~(1 << 15);
635 }
636
637 p->dma_write(l, CLNK_CTRL, lch);
638 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
639 }
640
641 static inline void omap2_enable_irq_lch(int lch)
642 {
643 u32 val;
644 unsigned long flags;
645
646 if (!cpu_class_is_omap2())
647 return;
648
649 spin_lock_irqsave(&dma_chan_lock, flags);
650 val = p->dma_read(IRQENABLE_L0, lch);
651 val |= 1 << lch;
652 p->dma_write(val, IRQENABLE_L0, lch);
653 spin_unlock_irqrestore(&dma_chan_lock, flags);
654 }
655
656 static inline void omap2_disable_irq_lch(int lch)
657 {
658 u32 val;
659 unsigned long flags;
660
661 if (!cpu_class_is_omap2())
662 return;
663
664 spin_lock_irqsave(&dma_chan_lock, flags);
665 val = p->dma_read(IRQENABLE_L0, lch);
666 val &= ~(1 << lch);
667 p->dma_write(val, IRQENABLE_L0, lch);
668 spin_unlock_irqrestore(&dma_chan_lock, flags);
669 }
670
671 int omap_request_dma(int dev_id, const char *dev_name,
672 void (*callback)(int lch, u16 ch_status, void *data),
673 void *data, int *dma_ch_out)
674 {
675 int ch, free_ch = -1;
676 unsigned long flags;
677 struct omap_dma_lch *chan;
678
679 spin_lock_irqsave(&dma_chan_lock, flags);
680 for (ch = 0; ch < dma_chan_count; ch++) {
681 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
682 free_ch = ch;
683 if (dev_id == 0)
684 break;
685 }
686 }
687 if (free_ch == -1) {
688 spin_unlock_irqrestore(&dma_chan_lock, flags);
689 return -EBUSY;
690 }
691 chan = dma_chan + free_ch;
692 chan->dev_id = dev_id;
693
694 if (p->clear_lch_regs)
695 p->clear_lch_regs(free_ch);
696
697 if (cpu_class_is_omap2())
698 omap_clear_dma(free_ch);
699
700 spin_unlock_irqrestore(&dma_chan_lock, flags);
701
702 chan->dev_name = dev_name;
703 chan->callback = callback;
704 chan->data = data;
705 chan->flags = 0;
706
707 #ifndef CONFIG_ARCH_OMAP1
708 if (cpu_class_is_omap2()) {
709 chan->chain_id = -1;
710 chan->next_linked_ch = -1;
711 }
712 #endif
713
714 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
715
716 if (cpu_class_is_omap1())
717 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
718 else if (cpu_class_is_omap2())
719 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
720 OMAP2_DMA_TRANS_ERR_IRQ;
721
722 if (cpu_is_omap16xx()) {
723 /* If the sync device is set, configure it dynamically. */
724 if (dev_id != 0) {
725 set_gdma_dev(free_ch + 1, dev_id);
726 dev_id = free_ch + 1;
727 }
728 /*
729 * Disable the 1510 compatibility mode and set the sync device
730 * id.
731 */
732 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
733 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
734 p->dma_write(dev_id, CCR, free_ch);
735 }
736
737 if (cpu_class_is_omap2()) {
738 omap2_enable_irq_lch(free_ch);
739 omap_enable_channel_irq(free_ch);
740 /* Clear the CSR register and IRQ status register */
741 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
742 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
743 }
744
745 *dma_ch_out = free_ch;
746
747 return 0;
748 }
749 EXPORT_SYMBOL(omap_request_dma);
750
751 void omap_free_dma(int lch)
752 {
753 unsigned long flags;
754
755 if (dma_chan[lch].dev_id == -1) {
756 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
757 lch);
758 return;
759 }
760
761 if (cpu_class_is_omap1()) {
762 /* Disable all DMA interrupts for the channel. */
763 p->dma_write(0, CICR, lch);
764 /* Make sure the DMA transfer is stopped. */
765 p->dma_write(0, CCR, lch);
766 }
767
768 if (cpu_class_is_omap2()) {
769 omap2_disable_irq_lch(lch);
770
771 /* Clear the CSR register and IRQ status register */
772 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
773 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
774
775 /* Disable all DMA interrupts for the channel. */
776 p->dma_write(0, CICR, lch);
777
778 /* Make sure the DMA transfer is stopped. */
779 p->dma_write(0, CCR, lch);
780 omap_clear_dma(lch);
781 }
782
783 spin_lock_irqsave(&dma_chan_lock, flags);
784 dma_chan[lch].dev_id = -1;
785 dma_chan[lch].next_lch = -1;
786 dma_chan[lch].callback = NULL;
787 spin_unlock_irqrestore(&dma_chan_lock, flags);
788 }
789 EXPORT_SYMBOL(omap_free_dma);
790
791 /**
792 * @brief omap_dma_set_global_params : Set global priority settings for dma
793 *
794 * @param arb_rate
795 * @param max_fifo_depth
796 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
797 * DMA_THREAD_RESERVE_ONET
798 * DMA_THREAD_RESERVE_TWOT
799 * DMA_THREAD_RESERVE_THREET
800 */
801 void
802 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
803 {
804 u32 reg;
805
806 if (!cpu_class_is_omap2()) {
807 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
808 return;
809 }
810
811 if (max_fifo_depth == 0)
812 max_fifo_depth = 1;
813 if (arb_rate == 0)
814 arb_rate = 1;
815
816 reg = 0xff & max_fifo_depth;
817 reg |= (0x3 & tparams) << 12;
818 reg |= (arb_rate & 0xff) << 16;
819
820 p->dma_write(reg, GCR, 0);
821 }
822 EXPORT_SYMBOL(omap_dma_set_global_params);
823
824 /**
825 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
826 *
827 * @param lch
828 * @param read_prio - Read priority
829 * @param write_prio - Write priority
830 * Both of the above can be set with one of the following values :
831 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
832 */
833 int
834 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
835 unsigned char write_prio)
836 {
837 u32 l;
838
839 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
840 printk(KERN_ERR "Invalid channel id\n");
841 return -EINVAL;
842 }
843 l = p->dma_read(CCR, lch);
844 l &= ~((1 << 6) | (1 << 26));
845 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
846 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
847 else
848 l |= ((read_prio & 0x1) << 6);
849
850 p->dma_write(l, CCR, lch);
851
852 return 0;
853 }
854 EXPORT_SYMBOL(omap_dma_set_prio_lch);
855
856 /*
857 * Clears any DMA state so the DMA engine is ready to restart with new buffers
858 * through omap_start_dma(). Any buffers in flight are discarded.
859 */
860 void omap_clear_dma(int lch)
861 {
862 unsigned long flags;
863
864 local_irq_save(flags);
865 p->clear_dma(lch);
866 local_irq_restore(flags);
867 }
868 EXPORT_SYMBOL(omap_clear_dma);
869
870 void omap_start_dma(int lch)
871 {
872 u32 l;
873
874 /*
875 * The CPC/CDAC register needs to be initialized to zero
876 * before starting dma transfer.
877 */
878 if (cpu_is_omap15xx())
879 p->dma_write(0, CPC, lch);
880 else
881 p->dma_write(0, CDAC, lch);
882
883 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
884 int next_lch, cur_lch;
885 char dma_chan_link_map[dma_lch_count];
886
887 dma_chan_link_map[lch] = 1;
888 /* Set the link register of the first channel */
889 enable_lnk(lch);
890
891 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
892 cur_lch = dma_chan[lch].next_lch;
893 do {
894 next_lch = dma_chan[cur_lch].next_lch;
895
896 /* The loop case: we've been here already */
897 if (dma_chan_link_map[cur_lch])
898 break;
899 /* Mark the current channel */
900 dma_chan_link_map[cur_lch] = 1;
901
902 enable_lnk(cur_lch);
903 omap_enable_channel_irq(cur_lch);
904
905 cur_lch = next_lch;
906 } while (next_lch != -1);
907 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
908 p->dma_write(lch, CLNK_CTRL, lch);
909
910 omap_enable_channel_irq(lch);
911
912 l = p->dma_read(CCR, lch);
913
914 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
915 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
916 l |= OMAP_DMA_CCR_EN;
917
918 p->dma_write(l, CCR, lch);
919
920 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
921 }
922 EXPORT_SYMBOL(omap_start_dma);
923
924 void omap_stop_dma(int lch)
925 {
926 u32 l;
927
928 /* Disable all interrupts on the channel */
929 if (cpu_class_is_omap1())
930 p->dma_write(0, CICR, lch);
931
932 l = p->dma_read(CCR, lch);
933 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
934 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
935 int i = 0;
936 u32 sys_cf;
937
938 /* Configure No-Standby */
939 l = p->dma_read(OCP_SYSCONFIG, lch);
940 sys_cf = l;
941 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
942 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
943 p->dma_write(l , OCP_SYSCONFIG, 0);
944
945 l = p->dma_read(CCR, lch);
946 l &= ~OMAP_DMA_CCR_EN;
947 p->dma_write(l, CCR, lch);
948
949 /* Wait for sDMA FIFO drain */
950 l = p->dma_read(CCR, lch);
951 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
952 OMAP_DMA_CCR_WR_ACTIVE))) {
953 udelay(5);
954 i++;
955 l = p->dma_read(CCR, lch);
956 }
957 if (i >= 100)
958 printk(KERN_ERR "DMA drain did not complete on "
959 "lch %d\n", lch);
960 /* Restore OCP_SYSCONFIG */
961 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
962 } else {
963 l &= ~OMAP_DMA_CCR_EN;
964 p->dma_write(l, CCR, lch);
965 }
966
967 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
968 int next_lch, cur_lch = lch;
969 char dma_chan_link_map[dma_lch_count];
970
971 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
972 do {
973 /* The loop case: we've been here already */
974 if (dma_chan_link_map[cur_lch])
975 break;
976 /* Mark the current channel */
977 dma_chan_link_map[cur_lch] = 1;
978
979 disable_lnk(cur_lch);
980
981 next_lch = dma_chan[cur_lch].next_lch;
982 cur_lch = next_lch;
983 } while (next_lch != -1);
984 }
985
986 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
987 }
988 EXPORT_SYMBOL(omap_stop_dma);
989
990 /*
991 * Allows changing the DMA callback function or data. This may be needed if
992 * the driver shares a single DMA channel for multiple dma triggers.
993 */
994 int omap_set_dma_callback(int lch,
995 void (*callback)(int lch, u16 ch_status, void *data),
996 void *data)
997 {
998 unsigned long flags;
999
1000 if (lch < 0)
1001 return -ENODEV;
1002
1003 spin_lock_irqsave(&dma_chan_lock, flags);
1004 if (dma_chan[lch].dev_id == -1) {
1005 printk(KERN_ERR "DMA callback for not set for free channel\n");
1006 spin_unlock_irqrestore(&dma_chan_lock, flags);
1007 return -EINVAL;
1008 }
1009 dma_chan[lch].callback = callback;
1010 dma_chan[lch].data = data;
1011 spin_unlock_irqrestore(&dma_chan_lock, flags);
1012
1013 return 0;
1014 }
1015 EXPORT_SYMBOL(omap_set_dma_callback);
1016
1017 /*
1018 * Returns current physical source address for the given DMA channel.
1019 * If the channel is running the caller must disable interrupts prior calling
1020 * this function and process the returned value before re-enabling interrupt to
1021 * prevent races with the interrupt handler. Note that in continuous mode there
1022 * is a chance for CSSA_L register overflow between the two reads resulting
1023 * in incorrect return value.
1024 */
1025 dma_addr_t omap_get_dma_src_pos(int lch)
1026 {
1027 dma_addr_t offset = 0;
1028
1029 if (cpu_is_omap15xx())
1030 offset = p->dma_read(CPC, lch);
1031 else
1032 offset = p->dma_read(CSAC, lch);
1033
1034 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1035 offset = p->dma_read(CSAC, lch);
1036
1037 if (!cpu_is_omap15xx()) {
1038 /*
1039 * CDAC == 0 indicates that the DMA transfer on the channel has
1040 * not been started (no data has been transferred so far).
1041 * Return the programmed source start address in this case.
1042 */
1043 if (likely(p->dma_read(CDAC, lch)))
1044 offset = p->dma_read(CSAC, lch);
1045 else
1046 offset = p->dma_read(CSSA, lch);
1047 }
1048
1049 if (cpu_class_is_omap1())
1050 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1051
1052 return offset;
1053 }
1054 EXPORT_SYMBOL(omap_get_dma_src_pos);
1055
1056 /*
1057 * Returns current physical destination address for the given DMA channel.
1058 * If the channel is running the caller must disable interrupts prior calling
1059 * this function and process the returned value before re-enabling interrupt to
1060 * prevent races with the interrupt handler. Note that in continuous mode there
1061 * is a chance for CDSA_L register overflow between the two reads resulting
1062 * in incorrect return value.
1063 */
1064 dma_addr_t omap_get_dma_dst_pos(int lch)
1065 {
1066 dma_addr_t offset = 0;
1067
1068 if (cpu_is_omap15xx())
1069 offset = p->dma_read(CPC, lch);
1070 else
1071 offset = p->dma_read(CDAC, lch);
1072
1073 /*
1074 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1075 * read before the DMA controller finished disabling the channel.
1076 */
1077 if (!cpu_is_omap15xx() && offset == 0) {
1078 offset = p->dma_read(CDAC, lch);
1079 /*
1080 * CDAC == 0 indicates that the DMA transfer on the channel has
1081 * not been started (no data has been transferred so far).
1082 * Return the programmed destination start address in this case.
1083 */
1084 if (unlikely(!offset))
1085 offset = p->dma_read(CDSA, lch);
1086 }
1087
1088 if (cpu_class_is_omap1())
1089 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1090
1091 return offset;
1092 }
1093 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1094
1095 int omap_get_dma_active_status(int lch)
1096 {
1097 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1098 }
1099 EXPORT_SYMBOL(omap_get_dma_active_status);
1100
1101 int omap_dma_running(void)
1102 {
1103 int lch;
1104
1105 if (cpu_class_is_omap1())
1106 if (omap_lcd_dma_running())
1107 return 1;
1108
1109 for (lch = 0; lch < dma_chan_count; lch++)
1110 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1111 return 1;
1112
1113 return 0;
1114 }
1115
1116 /*
1117 * lch_queue DMA will start right after lch_head one is finished.
1118 * For this DMA link to start, you still need to start (see omap_start_dma)
1119 * the first one. That will fire up the entire queue.
1120 */
1121 void omap_dma_link_lch(int lch_head, int lch_queue)
1122 {
1123 if (omap_dma_in_1510_mode()) {
1124 if (lch_head == lch_queue) {
1125 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1126 CCR, lch_head);
1127 return;
1128 }
1129 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1130 BUG();
1131 return;
1132 }
1133
1134 if ((dma_chan[lch_head].dev_id == -1) ||
1135 (dma_chan[lch_queue].dev_id == -1)) {
1136 printk(KERN_ERR "omap_dma: trying to link "
1137 "non requested channels\n");
1138 dump_stack();
1139 }
1140
1141 dma_chan[lch_head].next_lch = lch_queue;
1142 }
1143 EXPORT_SYMBOL(omap_dma_link_lch);
1144
1145 /*
1146 * Once the DMA queue is stopped, we can destroy it.
1147 */
1148 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1149 {
1150 if (omap_dma_in_1510_mode()) {
1151 if (lch_head == lch_queue) {
1152 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1153 CCR, lch_head);
1154 return;
1155 }
1156 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1157 BUG();
1158 return;
1159 }
1160
1161 if (dma_chan[lch_head].next_lch != lch_queue ||
1162 dma_chan[lch_head].next_lch == -1) {
1163 printk(KERN_ERR "omap_dma: trying to unlink "
1164 "non linked channels\n");
1165 dump_stack();
1166 }
1167
1168 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1169 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1170 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1171 "before unlinking\n");
1172 dump_stack();
1173 }
1174
1175 dma_chan[lch_head].next_lch = -1;
1176 }
1177 EXPORT_SYMBOL(omap_dma_unlink_lch);
1178
1179 #ifndef CONFIG_ARCH_OMAP1
1180 /* Create chain of DMA channesls */
1181 static void create_dma_lch_chain(int lch_head, int lch_queue)
1182 {
1183 u32 l;
1184
1185 /* Check if this is the first link in chain */
1186 if (dma_chan[lch_head].next_linked_ch == -1) {
1187 dma_chan[lch_head].next_linked_ch = lch_queue;
1188 dma_chan[lch_head].prev_linked_ch = lch_queue;
1189 dma_chan[lch_queue].next_linked_ch = lch_head;
1190 dma_chan[lch_queue].prev_linked_ch = lch_head;
1191 }
1192
1193 /* a link exists, link the new channel in circular chain */
1194 else {
1195 dma_chan[lch_queue].next_linked_ch =
1196 dma_chan[lch_head].next_linked_ch;
1197 dma_chan[lch_queue].prev_linked_ch = lch_head;
1198 dma_chan[lch_head].next_linked_ch = lch_queue;
1199 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1200 lch_queue;
1201 }
1202
1203 l = p->dma_read(CLNK_CTRL, lch_head);
1204 l &= ~(0x1f);
1205 l |= lch_queue;
1206 p->dma_write(l, CLNK_CTRL, lch_head);
1207
1208 l = p->dma_read(CLNK_CTRL, lch_queue);
1209 l &= ~(0x1f);
1210 l |= (dma_chan[lch_queue].next_linked_ch);
1211 p->dma_write(l, CLNK_CTRL, lch_queue);
1212 }
1213
1214 /**
1215 * @brief omap_request_dma_chain : Request a chain of DMA channels
1216 *
1217 * @param dev_id - Device id using the dma channel
1218 * @param dev_name - Device name
1219 * @param callback - Call back function
1220 * @chain_id -
1221 * @no_of_chans - Number of channels requested
1222 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1223 * OMAP_DMA_DYNAMIC_CHAIN
1224 * @params - Channel parameters
1225 *
1226 * @return - Success : 0
1227 * Failure: -EINVAL/-ENOMEM
1228 */
1229 int omap_request_dma_chain(int dev_id, const char *dev_name,
1230 void (*callback) (int lch, u16 ch_status,
1231 void *data),
1232 int *chain_id, int no_of_chans, int chain_mode,
1233 struct omap_dma_channel_params params)
1234 {
1235 int *channels;
1236 int i, err;
1237
1238 /* Is the chain mode valid ? */
1239 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1240 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1241 printk(KERN_ERR "Invalid chain mode requested\n");
1242 return -EINVAL;
1243 }
1244
1245 if (unlikely((no_of_chans < 1
1246 || no_of_chans > dma_lch_count))) {
1247 printk(KERN_ERR "Invalid Number of channels requested\n");
1248 return -EINVAL;
1249 }
1250
1251 /*
1252 * Allocate a queue to maintain the status of the channels
1253 * in the chain
1254 */
1255 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1256 if (channels == NULL) {
1257 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1258 return -ENOMEM;
1259 }
1260
1261 /* request and reserve DMA channels for the chain */
1262 for (i = 0; i < no_of_chans; i++) {
1263 err = omap_request_dma(dev_id, dev_name,
1264 callback, NULL, &channels[i]);
1265 if (err < 0) {
1266 int j;
1267 for (j = 0; j < i; j++)
1268 omap_free_dma(channels[j]);
1269 kfree(channels);
1270 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1271 return err;
1272 }
1273 dma_chan[channels[i]].prev_linked_ch = -1;
1274 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1275
1276 /*
1277 * Allowing client drivers to set common parameters now,
1278 * so that later only relevant (src_start, dest_start
1279 * and element count) can be set
1280 */
1281 omap_set_dma_params(channels[i], &params);
1282 }
1283
1284 *chain_id = channels[0];
1285 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1286 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1287 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1288 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1289
1290 for (i = 0; i < no_of_chans; i++)
1291 dma_chan[channels[i]].chain_id = *chain_id;
1292
1293 /* Reset the Queue pointers */
1294 OMAP_DMA_CHAIN_QINIT(*chain_id);
1295
1296 /* Set up the chain */
1297 if (no_of_chans == 1)
1298 create_dma_lch_chain(channels[0], channels[0]);
1299 else {
1300 for (i = 0; i < (no_of_chans - 1); i++)
1301 create_dma_lch_chain(channels[i], channels[i + 1]);
1302 }
1303
1304 return 0;
1305 }
1306 EXPORT_SYMBOL(omap_request_dma_chain);
1307
1308 /**
1309 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1310 * params after setting it. Dont do this while dma is running!!
1311 *
1312 * @param chain_id - Chained logical channel id.
1313 * @param params
1314 *
1315 * @return - Success : 0
1316 * Failure : -EINVAL
1317 */
1318 int omap_modify_dma_chain_params(int chain_id,
1319 struct omap_dma_channel_params params)
1320 {
1321 int *channels;
1322 u32 i;
1323
1324 /* Check for input params */
1325 if (unlikely((chain_id < 0
1326 || chain_id >= dma_lch_count))) {
1327 printk(KERN_ERR "Invalid chain id\n");
1328 return -EINVAL;
1329 }
1330
1331 /* Check if the chain exists */
1332 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1333 printk(KERN_ERR "Chain doesn't exists\n");
1334 return -EINVAL;
1335 }
1336 channels = dma_linked_lch[chain_id].linked_dmach_q;
1337
1338 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1339 /*
1340 * Allowing client drivers to set common parameters now,
1341 * so that later only relevant (src_start, dest_start
1342 * and element count) can be set
1343 */
1344 omap_set_dma_params(channels[i], &params);
1345 }
1346
1347 return 0;
1348 }
1349 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1350
1351 /**
1352 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1353 *
1354 * @param chain_id
1355 *
1356 * @return - Success : 0
1357 * Failure : -EINVAL
1358 */
1359 int omap_free_dma_chain(int chain_id)
1360 {
1361 int *channels;
1362 u32 i;
1363
1364 /* Check for input params */
1365 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1366 printk(KERN_ERR "Invalid chain id\n");
1367 return -EINVAL;
1368 }
1369
1370 /* Check if the chain exists */
1371 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1372 printk(KERN_ERR "Chain doesn't exists\n");
1373 return -EINVAL;
1374 }
1375
1376 channels = dma_linked_lch[chain_id].linked_dmach_q;
1377 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1378 dma_chan[channels[i]].next_linked_ch = -1;
1379 dma_chan[channels[i]].prev_linked_ch = -1;
1380 dma_chan[channels[i]].chain_id = -1;
1381 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1382 omap_free_dma(channels[i]);
1383 }
1384
1385 kfree(channels);
1386
1387 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1388 dma_linked_lch[chain_id].chain_mode = -1;
1389 dma_linked_lch[chain_id].chain_state = -1;
1390
1391 return (0);
1392 }
1393 EXPORT_SYMBOL(omap_free_dma_chain);
1394
1395 /**
1396 * @brief omap_dma_chain_status - Check if the chain is in
1397 * active / inactive state.
1398 * @param chain_id
1399 *
1400 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1401 * Failure : -EINVAL
1402 */
1403 int omap_dma_chain_status(int chain_id)
1404 {
1405 /* Check for input params */
1406 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1407 printk(KERN_ERR "Invalid chain id\n");
1408 return -EINVAL;
1409 }
1410
1411 /* Check if the chain exists */
1412 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1413 printk(KERN_ERR "Chain doesn't exists\n");
1414 return -EINVAL;
1415 }
1416 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1417 dma_linked_lch[chain_id].q_count);
1418
1419 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1420 return OMAP_DMA_CHAIN_INACTIVE;
1421
1422 return OMAP_DMA_CHAIN_ACTIVE;
1423 }
1424 EXPORT_SYMBOL(omap_dma_chain_status);
1425
1426 /**
1427 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1428 * set the params and start the transfer.
1429 *
1430 * @param chain_id
1431 * @param src_start - buffer start address
1432 * @param dest_start - Dest address
1433 * @param elem_count
1434 * @param frame_count
1435 * @param callbk_data - channel callback parameter data.
1436 *
1437 * @return - Success : 0
1438 * Failure: -EINVAL/-EBUSY
1439 */
1440 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1441 int elem_count, int frame_count, void *callbk_data)
1442 {
1443 int *channels;
1444 u32 l, lch;
1445 int start_dma = 0;
1446
1447 /*
1448 * if buffer size is less than 1 then there is
1449 * no use of starting the chain
1450 */
1451 if (elem_count < 1) {
1452 printk(KERN_ERR "Invalid buffer size\n");
1453 return -EINVAL;
1454 }
1455
1456 /* Check for input params */
1457 if (unlikely((chain_id < 0
1458 || chain_id >= dma_lch_count))) {
1459 printk(KERN_ERR "Invalid chain id\n");
1460 return -EINVAL;
1461 }
1462
1463 /* Check if the chain exists */
1464 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1465 printk(KERN_ERR "Chain doesn't exist\n");
1466 return -EINVAL;
1467 }
1468
1469 /* Check if all the channels in chain are in use */
1470 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1471 return -EBUSY;
1472
1473 /* Frame count may be negative in case of indexed transfers */
1474 channels = dma_linked_lch[chain_id].linked_dmach_q;
1475
1476 /* Get a free channel */
1477 lch = channels[dma_linked_lch[chain_id].q_tail];
1478
1479 /* Store the callback data */
1480 dma_chan[lch].data = callbk_data;
1481
1482 /* Increment the q_tail */
1483 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1484
1485 /* Set the params to the free channel */
1486 if (src_start != 0)
1487 p->dma_write(src_start, CSSA, lch);
1488 if (dest_start != 0)
1489 p->dma_write(dest_start, CDSA, lch);
1490
1491 /* Write the buffer size */
1492 p->dma_write(elem_count, CEN, lch);
1493 p->dma_write(frame_count, CFN, lch);
1494
1495 /*
1496 * If the chain is dynamically linked,
1497 * then we may have to start the chain if its not active
1498 */
1499 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1500
1501 /*
1502 * In Dynamic chain, if the chain is not started,
1503 * queue the channel
1504 */
1505 if (dma_linked_lch[chain_id].chain_state ==
1506 DMA_CHAIN_NOTSTARTED) {
1507 /* Enable the link in previous channel */
1508 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1509 DMA_CH_QUEUED)
1510 enable_lnk(dma_chan[lch].prev_linked_ch);
1511 dma_chan[lch].state = DMA_CH_QUEUED;
1512 }
1513
1514 /*
1515 * Chain is already started, make sure its active,
1516 * if not then start the chain
1517 */
1518 else {
1519 start_dma = 1;
1520
1521 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1522 DMA_CH_STARTED) {
1523 enable_lnk(dma_chan[lch].prev_linked_ch);
1524 dma_chan[lch].state = DMA_CH_QUEUED;
1525 start_dma = 0;
1526 if (0 == ((1 << 7) & p->dma_read(
1527 CCR, dma_chan[lch].prev_linked_ch))) {
1528 disable_lnk(dma_chan[lch].
1529 prev_linked_ch);
1530 pr_debug("\n prev ch is stopped\n");
1531 start_dma = 1;
1532 }
1533 }
1534
1535 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1536 == DMA_CH_QUEUED) {
1537 enable_lnk(dma_chan[lch].prev_linked_ch);
1538 dma_chan[lch].state = DMA_CH_QUEUED;
1539 start_dma = 0;
1540 }
1541 omap_enable_channel_irq(lch);
1542
1543 l = p->dma_read(CCR, lch);
1544
1545 if ((0 == (l & (1 << 24))))
1546 l &= ~(1 << 25);
1547 else
1548 l |= (1 << 25);
1549 if (start_dma == 1) {
1550 if (0 == (l & (1 << 7))) {
1551 l |= (1 << 7);
1552 dma_chan[lch].state = DMA_CH_STARTED;
1553 pr_debug("starting %d\n", lch);
1554 p->dma_write(l, CCR, lch);
1555 } else
1556 start_dma = 0;
1557 } else {
1558 if (0 == (l & (1 << 7)))
1559 p->dma_write(l, CCR, lch);
1560 }
1561 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1562 }
1563 }
1564
1565 return 0;
1566 }
1567 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1568
1569 /**
1570 * @brief omap_start_dma_chain_transfers - Start the chain
1571 *
1572 * @param chain_id
1573 *
1574 * @return - Success : 0
1575 * Failure : -EINVAL/-EBUSY
1576 */
1577 int omap_start_dma_chain_transfers(int chain_id)
1578 {
1579 int *channels;
1580 u32 l, i;
1581
1582 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1583 printk(KERN_ERR "Invalid chain id\n");
1584 return -EINVAL;
1585 }
1586
1587 channels = dma_linked_lch[chain_id].linked_dmach_q;
1588
1589 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1590 printk(KERN_ERR "Chain is already started\n");
1591 return -EBUSY;
1592 }
1593
1594 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1595 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1596 i++) {
1597 enable_lnk(channels[i]);
1598 omap_enable_channel_irq(channels[i]);
1599 }
1600 } else {
1601 omap_enable_channel_irq(channels[0]);
1602 }
1603
1604 l = p->dma_read(CCR, channels[0]);
1605 l |= (1 << 7);
1606 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1607 dma_chan[channels[0]].state = DMA_CH_STARTED;
1608
1609 if ((0 == (l & (1 << 24))))
1610 l &= ~(1 << 25);
1611 else
1612 l |= (1 << 25);
1613 p->dma_write(l, CCR, channels[0]);
1614
1615 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1616
1617 return 0;
1618 }
1619 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1620
1621 /**
1622 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1623 *
1624 * @param chain_id
1625 *
1626 * @return - Success : 0
1627 * Failure : EINVAL
1628 */
1629 int omap_stop_dma_chain_transfers(int chain_id)
1630 {
1631 int *channels;
1632 u32 l, i;
1633 u32 sys_cf = 0;
1634
1635 /* Check for input params */
1636 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1637 printk(KERN_ERR "Invalid chain id\n");
1638 return -EINVAL;
1639 }
1640
1641 /* Check if the chain exists */
1642 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1643 printk(KERN_ERR "Chain doesn't exists\n");
1644 return -EINVAL;
1645 }
1646 channels = dma_linked_lch[chain_id].linked_dmach_q;
1647
1648 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1649 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1650 l = sys_cf;
1651 /* Middle mode reg set no Standby */
1652 l &= ~((1 << 12)|(1 << 13));
1653 p->dma_write(l, OCP_SYSCONFIG, 0);
1654 }
1655
1656 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1657
1658 /* Stop the Channel transmission */
1659 l = p->dma_read(CCR, channels[i]);
1660 l &= ~(1 << 7);
1661 p->dma_write(l, CCR, channels[i]);
1662
1663 /* Disable the link in all the channels */
1664 disable_lnk(channels[i]);
1665 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1666
1667 }
1668 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1669
1670 /* Reset the Queue pointers */
1671 OMAP_DMA_CHAIN_QINIT(chain_id);
1672
1673 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1674 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1675
1676 return 0;
1677 }
1678 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1679
1680 /* Get the index of the ongoing DMA in chain */
1681 /**
1682 * @brief omap_get_dma_chain_index - Get the element and frame index
1683 * of the ongoing DMA in chain
1684 *
1685 * @param chain_id
1686 * @param ei - Element index
1687 * @param fi - Frame index
1688 *
1689 * @return - Success : 0
1690 * Failure : -EINVAL
1691 */
1692 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1693 {
1694 int lch;
1695 int *channels;
1696
1697 /* Check for input params */
1698 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1699 printk(KERN_ERR "Invalid chain id\n");
1700 return -EINVAL;
1701 }
1702
1703 /* Check if the chain exists */
1704 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1705 printk(KERN_ERR "Chain doesn't exists\n");
1706 return -EINVAL;
1707 }
1708 if ((!ei) || (!fi))
1709 return -EINVAL;
1710
1711 channels = dma_linked_lch[chain_id].linked_dmach_q;
1712
1713 /* Get the current channel */
1714 lch = channels[dma_linked_lch[chain_id].q_head];
1715
1716 *ei = p->dma_read(CCEN, lch);
1717 *fi = p->dma_read(CCFN, lch);
1718
1719 return 0;
1720 }
1721 EXPORT_SYMBOL(omap_get_dma_chain_index);
1722
1723 /**
1724 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1725 * ongoing DMA in chain
1726 *
1727 * @param chain_id
1728 *
1729 * @return - Success : Destination position
1730 * Failure : -EINVAL
1731 */
1732 int omap_get_dma_chain_dst_pos(int chain_id)
1733 {
1734 int lch;
1735 int *channels;
1736
1737 /* Check for input params */
1738 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1739 printk(KERN_ERR "Invalid chain id\n");
1740 return -EINVAL;
1741 }
1742
1743 /* Check if the chain exists */
1744 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1745 printk(KERN_ERR "Chain doesn't exists\n");
1746 return -EINVAL;
1747 }
1748
1749 channels = dma_linked_lch[chain_id].linked_dmach_q;
1750
1751 /* Get the current channel */
1752 lch = channels[dma_linked_lch[chain_id].q_head];
1753
1754 return p->dma_read(CDAC, lch);
1755 }
1756 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1757
1758 /**
1759 * @brief omap_get_dma_chain_src_pos - Get the source position
1760 * of the ongoing DMA in chain
1761 * @param chain_id
1762 *
1763 * @return - Success : Destination position
1764 * Failure : -EINVAL
1765 */
1766 int omap_get_dma_chain_src_pos(int chain_id)
1767 {
1768 int lch;
1769 int *channels;
1770
1771 /* Check for input params */
1772 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1773 printk(KERN_ERR "Invalid chain id\n");
1774 return -EINVAL;
1775 }
1776
1777 /* Check if the chain exists */
1778 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1779 printk(KERN_ERR "Chain doesn't exists\n");
1780 return -EINVAL;
1781 }
1782
1783 channels = dma_linked_lch[chain_id].linked_dmach_q;
1784
1785 /* Get the current channel */
1786 lch = channels[dma_linked_lch[chain_id].q_head];
1787
1788 return p->dma_read(CSAC, lch);
1789 }
1790 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1791 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1792
1793 /*----------------------------------------------------------------------------*/
1794
1795 #ifdef CONFIG_ARCH_OMAP1
1796
1797 static int omap1_dma_handle_ch(int ch)
1798 {
1799 u32 csr;
1800
1801 if (enable_1510_mode && ch >= 6) {
1802 csr = dma_chan[ch].saved_csr;
1803 dma_chan[ch].saved_csr = 0;
1804 } else
1805 csr = p->dma_read(CSR, ch);
1806 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1807 dma_chan[ch + 6].saved_csr = csr >> 7;
1808 csr &= 0x7f;
1809 }
1810 if ((csr & 0x3f) == 0)
1811 return 0;
1812 if (unlikely(dma_chan[ch].dev_id == -1)) {
1813 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1814 "%d (CSR %04x)\n", ch, csr);
1815 return 0;
1816 }
1817 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1818 printk(KERN_WARNING "DMA timeout with device %d\n",
1819 dma_chan[ch].dev_id);
1820 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1821 printk(KERN_WARNING "DMA synchronization event drop occurred "
1822 "with device %d\n", dma_chan[ch].dev_id);
1823 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1824 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1825 if (likely(dma_chan[ch].callback != NULL))
1826 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1827
1828 return 1;
1829 }
1830
1831 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1832 {
1833 int ch = ((int) dev_id) - 1;
1834 int handled = 0;
1835
1836 for (;;) {
1837 int handled_now = 0;
1838
1839 handled_now += omap1_dma_handle_ch(ch);
1840 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1841 handled_now += omap1_dma_handle_ch(ch + 6);
1842 if (!handled_now)
1843 break;
1844 handled += handled_now;
1845 }
1846
1847 return handled ? IRQ_HANDLED : IRQ_NONE;
1848 }
1849
1850 #else
1851 #define omap1_dma_irq_handler NULL
1852 #endif
1853
1854 #ifdef CONFIG_ARCH_OMAP2PLUS
1855
1856 static int omap2_dma_handle_ch(int ch)
1857 {
1858 u32 status = p->dma_read(CSR, ch);
1859
1860 if (!status) {
1861 if (printk_ratelimit())
1862 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1863 ch);
1864 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1865 return 0;
1866 }
1867 if (unlikely(dma_chan[ch].dev_id == -1)) {
1868 if (printk_ratelimit())
1869 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1870 "channel %d\n", status, ch);
1871 return 0;
1872 }
1873 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1874 printk(KERN_INFO
1875 "DMA synchronization event drop occurred with device "
1876 "%d\n", dma_chan[ch].dev_id);
1877 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1878 printk(KERN_INFO "DMA transaction error with device %d\n",
1879 dma_chan[ch].dev_id);
1880 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1881 u32 ccr;
1882
1883 ccr = p->dma_read(CCR, ch);
1884 ccr &= ~OMAP_DMA_CCR_EN;
1885 p->dma_write(ccr, CCR, ch);
1886 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1887 }
1888 }
1889 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1890 printk(KERN_INFO "DMA secure error with device %d\n",
1891 dma_chan[ch].dev_id);
1892 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1893 printk(KERN_INFO "DMA misaligned error with device %d\n",
1894 dma_chan[ch].dev_id);
1895
1896 p->dma_write(status, CSR, ch);
1897 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1898 /* read back the register to flush the write */
1899 p->dma_read(IRQSTATUS_L0, ch);
1900
1901 /* If the ch is not chained then chain_id will be -1 */
1902 if (dma_chan[ch].chain_id != -1) {
1903 int chain_id = dma_chan[ch].chain_id;
1904 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1905 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1906 dma_chan[dma_chan[ch].next_linked_ch].state =
1907 DMA_CH_STARTED;
1908 if (dma_linked_lch[chain_id].chain_mode ==
1909 OMAP_DMA_DYNAMIC_CHAIN)
1910 disable_lnk(ch);
1911
1912 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1913 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1914
1915 status = p->dma_read(CSR, ch);
1916 p->dma_write(status, CSR, ch);
1917 }
1918
1919 if (likely(dma_chan[ch].callback != NULL))
1920 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1921
1922 return 0;
1923 }
1924
1925 /* STATUS register count is from 1-32 while our is 0-31 */
1926 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1927 {
1928 u32 val, enable_reg;
1929 int i;
1930
1931 val = p->dma_read(IRQSTATUS_L0, 0);
1932 if (val == 0) {
1933 if (printk_ratelimit())
1934 printk(KERN_WARNING "Spurious DMA IRQ\n");
1935 return IRQ_HANDLED;
1936 }
1937 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1938 val &= enable_reg; /* Dispatch only relevant interrupts */
1939 for (i = 0; i < dma_lch_count && val != 0; i++) {
1940 if (val & 1)
1941 omap2_dma_handle_ch(i);
1942 val >>= 1;
1943 }
1944
1945 return IRQ_HANDLED;
1946 }
1947
1948 static struct irqaction omap24xx_dma_irq = {
1949 .name = "DMA",
1950 .handler = omap2_dma_irq_handler,
1951 .flags = IRQF_DISABLED
1952 };
1953
1954 #else
1955 static struct irqaction omap24xx_dma_irq;
1956 #endif
1957
1958 /*----------------------------------------------------------------------------*/
1959
1960 void omap_dma_global_context_save(void)
1961 {
1962 omap_dma_global_context.dma_irqenable_l0 =
1963 p->dma_read(IRQENABLE_L0, 0);
1964 omap_dma_global_context.dma_ocp_sysconfig =
1965 p->dma_read(OCP_SYSCONFIG, 0);
1966 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1967 }
1968
1969 void omap_dma_global_context_restore(void)
1970 {
1971 int ch;
1972
1973 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1974 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1975 OCP_SYSCONFIG, 0);
1976 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1977 IRQENABLE_L0, 0);
1978
1979 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1980 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1981
1982 for (ch = 0; ch < dma_chan_count; ch++)
1983 if (dma_chan[ch].dev_id != -1)
1984 omap_clear_dma(ch);
1985 }
1986
1987 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1988 {
1989 int ch, ret = 0;
1990 int dma_irq;
1991 char irq_name[4];
1992 int irq_rel;
1993
1994 p = pdev->dev.platform_data;
1995 if (!p) {
1996 dev_err(&pdev->dev, "%s: System DMA initialized without"
1997 "platform data\n", __func__);
1998 return -EINVAL;
1999 }
2000
2001 d = p->dma_attr;
2002 errata = p->errata;
2003
2004 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2005 && (omap_dma_reserve_channels <= dma_lch_count))
2006 d->lch_count = omap_dma_reserve_channels;
2007
2008 dma_lch_count = d->lch_count;
2009 dma_chan_count = dma_lch_count;
2010 dma_chan = d->chan;
2011 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2012
2013 if (cpu_class_is_omap2()) {
2014 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2015 dma_lch_count, GFP_KERNEL);
2016 if (!dma_linked_lch) {
2017 ret = -ENOMEM;
2018 goto exit_dma_lch_fail;
2019 }
2020 }
2021
2022 spin_lock_init(&dma_chan_lock);
2023 for (ch = 0; ch < dma_chan_count; ch++) {
2024 omap_clear_dma(ch);
2025 if (cpu_class_is_omap2())
2026 omap2_disable_irq_lch(ch);
2027
2028 dma_chan[ch].dev_id = -1;
2029 dma_chan[ch].next_lch = -1;
2030
2031 if (ch >= 6 && enable_1510_mode)
2032 continue;
2033
2034 if (cpu_class_is_omap1()) {
2035 /*
2036 * request_irq() doesn't like dev_id (ie. ch) being
2037 * zero, so we have to kludge around this.
2038 */
2039 sprintf(&irq_name[0], "%d", ch);
2040 dma_irq = platform_get_irq_byname(pdev, irq_name);
2041
2042 if (dma_irq < 0) {
2043 ret = dma_irq;
2044 goto exit_dma_irq_fail;
2045 }
2046
2047 /* INT_DMA_LCD is handled in lcd_dma.c */
2048 if (dma_irq == INT_DMA_LCD)
2049 continue;
2050
2051 ret = request_irq(dma_irq,
2052 omap1_dma_irq_handler, 0, "DMA",
2053 (void *) (ch + 1));
2054 if (ret != 0)
2055 goto exit_dma_irq_fail;
2056 }
2057 }
2058
2059 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2060 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2061 DMA_DEFAULT_FIFO_DEPTH, 0);
2062
2063 if (cpu_class_is_omap2()) {
2064 strcpy(irq_name, "0");
2065 dma_irq = platform_get_irq_byname(pdev, irq_name);
2066 if (dma_irq < 0) {
2067 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2068 goto exit_dma_lch_fail;
2069 }
2070 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2071 if (ret) {
2072 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2073 "for DMA (error %d)\n", dma_irq, ret);
2074 goto exit_dma_lch_fail;
2075 }
2076 }
2077
2078 /* reserve dma channels 0 and 1 in high security devices */
2079 if (cpu_is_omap34xx() &&
2080 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2081 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2082 "HS ROM code\n");
2083 dma_chan[0].dev_id = 0;
2084 dma_chan[1].dev_id = 1;
2085 }
2086 p->show_dma_caps();
2087 return 0;
2088
2089 exit_dma_irq_fail:
2090 dev_err(&pdev->dev, "unable to request IRQ %d"
2091 "for DMA (error %d)\n", dma_irq, ret);
2092 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2093 dma_irq = platform_get_irq(pdev, irq_rel);
2094 free_irq(dma_irq, (void *)(irq_rel + 1));
2095 }
2096
2097 exit_dma_lch_fail:
2098 kfree(p);
2099 kfree(d);
2100 kfree(dma_chan);
2101 return ret;
2102 }
2103
2104 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2105 {
2106 int dma_irq;
2107
2108 if (cpu_class_is_omap2()) {
2109 char irq_name[4];
2110 strcpy(irq_name, "0");
2111 dma_irq = platform_get_irq_byname(pdev, irq_name);
2112 remove_irq(dma_irq, &omap24xx_dma_irq);
2113 } else {
2114 int irq_rel = 0;
2115 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2116 dma_irq = platform_get_irq(pdev, irq_rel);
2117 free_irq(dma_irq, (void *)(irq_rel + 1));
2118 }
2119 }
2120 kfree(p);
2121 kfree(d);
2122 kfree(dma_chan);
2123 return 0;
2124 }
2125
2126 static struct platform_driver omap_system_dma_driver = {
2127 .probe = omap_system_dma_probe,
2128 .remove = omap_system_dma_remove,
2129 .driver = {
2130 .name = "omap_dma_system"
2131 },
2132 };
2133
2134 static int __init omap_system_dma_init(void)
2135 {
2136 return platform_driver_register(&omap_system_dma_driver);
2137 }
2138 arch_initcall(omap_system_dma_init);
2139
2140 static void __exit omap_system_dma_exit(void)
2141 {
2142 platform_driver_unregister(&omap_system_dma_driver);
2143 }
2144
2145 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2146 MODULE_LICENSE("GPL");
2147 MODULE_ALIAS("platform:" DRIVER_NAME);
2148 MODULE_AUTHOR("Texas Instruments Inc");
2149
2150 /*
2151 * Reserve the omap SDMA channels using cmdline bootarg
2152 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2153 */
2154 static int __init omap_dma_cmdline_reserve_ch(char *str)
2155 {
2156 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2157 omap_dma_reserve_channels = 0;
2158 return 1;
2159 }
2160
2161 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2162
2163