arch/arm/plat-omap/include/plat/omap-serial.h

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #ifndef __OMAP_SERIAL_H__
  18 #define __OMAP_SERIAL_H__
  19
  20 #include <linux/serial_core.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_qos.h>
  23
  24 #include <plat/mux.h>
  25
  26 #define DRIVER_NAME     "omap_uart"
  27
  28 /*
  29  * Use tty device name as ttyO, [O -> OMAP]
  30  * in bootargs we specify as console=ttyO0 if uart1
  31  * is used as console uart.
  32  */
  33 #define OMAP_SERIAL_NAME        "ttyO"
  34
  35 #define OMAP_MODE13X_SPEED      230400
  36
  37 #define OMAP_UART_SCR_TX_EMPTY  0x08
  38
  39 /* WER = 0x7F
  40  * Enable module level wakeup in WER reg
  41  */
  42 #define OMAP_UART_WER_MOD_WKUP  0X7F
  43
  44 /* Enable XON/XOFF flow control on output */
  45 #define OMAP_UART_SW_TX         0x04
  46
  47 /* Enable XON/XOFF flow control on input */
  48 #define OMAP_UART_SW_RX         0x04
  49
  50 #define OMAP_UART_SYSC_RESET    0X07
  51 #define OMAP_UART_TCR_TRIG      0X0F
  52 #define OMAP_UART_SW_CLR        0XF0
  53 #define OMAP_UART_FIFO_CLR      0X06
  54
  55 #define OMAP_UART_DMA_CH_FREE   -1
  56
  57 #define OMAP_MAX_HSUART_PORTS   4
  58
  59 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  60
  61 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  62 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  63
  64 struct omap_uart_port_info {
  65         bool                    dma_enabled;    /* To specify DMA Mode */
  66         unsigned int            uartclk;        /* UART clock rate */
  67         upf_t                   flags;          /* UPF_* flags */
  68         u32                     errata;
  69         unsigned int            dma_rx_buf_size;
  70         unsigned int            dma_rx_timeout;
  71         unsigned int            autosuspend_timeout;
  72         unsigned int            dma_rx_poll_rate;
  73
  74         int (*get_context_loss_count)(struct device *);
  75         void (*set_forceidle)(struct platform_device *);
  76         void (*set_noidle)(struct platform_device *);
  77         void (*enable_wakeup)(struct platform_device *, bool);
  78 };
  79
  80 struct uart_omap_dma {
  81         u8                      uart_dma_tx;
  82         u8                      uart_dma_rx;
  83         int                     rx_dma_channel;
  84         int                     tx_dma_channel;
  85         dma_addr_t              rx_buf_dma_phys;
  86         dma_addr_t              tx_buf_dma_phys;
  87         unsigned int            uart_base;
  88         /*
  89          * Buffer for rx dma.It is not required for tx because the buffer
  90          * comes from port structure.
  91          */
  92         unsigned char           *rx_buf;
  93         unsigned int            prev_rx_dma_pos;
  94         int                     tx_buf_size;
  95         int                     tx_dma_used;
  96         int                     rx_dma_used;
  97         spinlock_t              tx_lock;
  98         spinlock_t              rx_lock;
  99         /* timer to poll activity on rx dma */
 100         struct timer_list       rx_timer;
 101         unsigned int            rx_buf_size;
 102         unsigned int            rx_poll_rate;
 103         unsigned int            rx_timeout;
 104 };
 105
 106 struct uart_omap_port {
 107         struct uart_port        port;
 108         struct uart_omap_dma    uart_dma;
 109         struct platform_device  *pdev;
 110
 111         unsigned char           ier;
 112         unsigned char           lcr;
 113         unsigned char           mcr;
 114         unsigned char           fcr;
 115         unsigned char           efr;
 116         unsigned char           dll;
 117         unsigned char           dlh;
 118         unsigned char           mdr1;
 119         unsigned char           scr;
 120
 121         int                     use_dma;
 122         /*
 123          * Some bits in registers are cleared on a read, so they must
 124          * be saved whenever the register is read but the bits will not
 125          * be immediately processed.
 126          */
 127         unsigned int            lsr_break_flag;
 128         unsigned char           msr_saved_flags;
 129         char                    name[20];
 130         unsigned long           port_activity;
 131         u32                     context_loss_cnt;
 132         u32                     errata;
 133         u8                      wakeups_enabled;
 134
 135         struct pm_qos_request   pm_qos_request;
 136         u32                     latency;
 137         u32                     calc_latency;
 138         struct work_struct      qos_work;
 139 };
 140
 141 #endif /* __OMAP_SERIAL_H__ */