spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / plat-orion / include / plat / pcie.h
blobfe5b9e8627475c6de0251b53ac2b803c9b01a286
1 /*
2 * arch/arm/plat-orion/include/plat/pcie.h
4 * Marvell Orion SoC PCIe handling.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
11 #ifndef __PLAT_PCIE_H
12 #define __PLAT_PCIE_H
14 struct pci_bus;
16 u32 orion_pcie_dev_id(void __iomem *base);
17 u32 orion_pcie_rev(void __iomem *base);
18 int orion_pcie_link_up(void __iomem *base);
19 int orion_pcie_x4_mode(void __iomem *base);
20 int orion_pcie_get_local_bus_nr(void __iomem *base);
21 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
22 void orion_pcie_reset(void __iomem *base);
23 void orion_pcie_setup(void __iomem *base);
24 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
25 u32 devfn, int where, int size, u32 *val);
26 int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
27 u32 devfn, int where, int size, u32 *val);
28 int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
29 u32 devfn, int where, int size, u32 *val);
30 int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
31 u32 devfn, int where, int size, u32 val);
34 #endif