spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / arm / plat-orion / irq.c
blob2d5b9c1ef3897778181d66b84b1a3281b6df24e2
1 /*
2 * arch/arm/plat-orion/irq.c
4 * Marvell Orion SoC IRQ handling.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/io.h>
15 #include <plat/irq.h>
17 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
19 struct irq_chip_generic *gc;
20 struct irq_chip_type *ct;
23 * Mask all interrupts initially.
25 writel(0, maskaddr);
27 gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
28 handle_level_irq);
29 ct = gc->chip_types;
30 ct->chip.irq_mask = irq_gc_mask_clr_bit;
31 ct->chip.irq_unmask = irq_gc_mask_set_bit;
32 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
33 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);