arch/arm/plat-versatile/platsmp.c

   1 /*
   2  *  linux/arch/arm/plat-versatile/platsmp.c
   3  *
   4  *  Copyright (C) 2002 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/smp.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/smp_plat.h>
  20 #include <asm/hardware/gic.h>
  21
  22 /*
  23  * control for which core is the next to come out of the secondary
  24  * boot "holding pen"
  25  */
  26 volatile int __cpuinitdata pen_release = -1;
  27
  28 /*
  29  * Write pen_release in a way that is guaranteed to be visible to all
  30  * observers, irrespective of whether they're taking part in coherency
  31  * or not.  This is necessary for the hotplug code to work reliably.
  32  */
  33 static void __cpuinit write_pen_release(int val)
  34 {
  35         pen_release = val;
  36         smp_wmb();
  37         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  38         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  39 }
  40
  41 static DEFINE_SPINLOCK(boot_lock);
  42
  43 void __cpuinit platform_secondary_init(unsigned int cpu)
  44 {
  45         /*
  46          * if any interrupts are already enabled for the primary
  47          * core (e.g. timer irq), then they will not have been enabled
  48          * for us: do so
  49          */
  50         gic_secondary_init(0);
  51
  52         /*
  53          * let the primary processor know we're out of the
  54          * pen, then head off into the C entry point
  55          */
  56         write_pen_release(-1);
  57
  58         /*
  59          * Synchronise with the boot thread.
  60          */
  61         spin_lock(&boot_lock);
  62         spin_unlock(&boot_lock);
  63 }
  64
  65 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  66 {
  67         unsigned long timeout;
  68
  69         /*
  70          * Set synchronisation state between this boot processor
  71          * and the secondary one
  72          */
  73         spin_lock(&boot_lock);
  74
  75         /*
  76          * This is really belt and braces; we hold unintended secondary
  77          * CPUs in the holding pen until we're ready for them.  However,
  78          * since we haven't sent them a soft interrupt, they shouldn't
  79          * be there.
  80          */
  81         write_pen_release(cpu_logical_map(cpu));
  82
  83         /*
  84          * Send the secondary CPU a soft interrupt, thereby causing
  85          * the boot monitor to read the system wide flags register,
  86          * and branch to the address found there.
  87          */
  88         gic_raise_softirq(cpumask_of(cpu), 1);
  89
  90         timeout = jiffies + (1 * HZ);
  91         while (time_before(jiffies, timeout)) {
  92                 smp_rmb();
  93                 if (pen_release == -1)
  94                         break;
  95
  96                 udelay(10);
  97         }
  98
  99         /*
 100          * now the secondary core is starting up let it run its
 101          * calibrations, then wait for it to finish
 102          */
 103         spin_unlock(&boot_lock);
 104
 105         return pen_release != -1 ? -ENOSYS : 0;
 106 }