spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / h8300 / platform / h8300h / irq.c
blobbc4f51bceef5e3927682feba994c78dc16e98dc5
1 /*
2 * Interrupt handling H8/300H depend.
3 * Yoshinori Sato <ysato@users.sourceforge.jp>
5 */
7 #include <linux/init.h>
8 #include <linux/errno.h>
10 #include <asm/ptrace.h>
11 #include <asm/traps.h>
12 #include <asm/irq.h>
13 #include <asm/io.h>
14 #include <asm/gpio-internal.h>
15 #include <asm/regs306x.h>
17 const int __initdata h8300_saved_vectors[] = {
18 #if defined(CONFIG_GDB_DEBUG)
19 TRAP3_VEC, /* TRAPA #3 is GDB breakpoint */
20 #endif
21 -1,
24 const h8300_vector __initdata h8300_trap_table[] = {
25 0, 0, 0, 0, 0, 0, 0, 0,
26 system_call,
29 trace_break,
32 int h8300_enable_irq_pin(unsigned int irq)
34 int bitmask;
35 if (irq < EXT_IRQ0 || irq > EXT_IRQ5)
36 return 0;
38 /* initialize IRQ pin */
39 bitmask = 1 << (irq - EXT_IRQ0);
40 switch(irq) {
41 case EXT_IRQ0:
42 case EXT_IRQ1:
43 case EXT_IRQ2:
44 case EXT_IRQ3:
45 if (H8300_GPIO_RESERVE(H8300_GPIO_P8, bitmask) == 0)
46 return -EBUSY;
47 H8300_GPIO_DDR(H8300_GPIO_P8, bitmask, H8300_GPIO_INPUT);
48 break;
49 case EXT_IRQ4:
50 case EXT_IRQ5:
51 if (H8300_GPIO_RESERVE(H8300_GPIO_P9, bitmask) == 0)
52 return -EBUSY;
53 H8300_GPIO_DDR(H8300_GPIO_P9, bitmask, H8300_GPIO_INPUT);
54 break;
57 return 0;
60 void h8300_disable_irq_pin(unsigned int irq)
62 int bitmask;
63 if (irq < EXT_IRQ0 || irq > EXT_IRQ5)
64 return;
66 /* disable interrupt & release IRQ pin */
67 bitmask = 1 << (irq - EXT_IRQ0);
68 switch(irq) {
69 case EXT_IRQ0:
70 case EXT_IRQ1:
71 case EXT_IRQ2:
72 case EXT_IRQ3:
73 *(volatile unsigned char *)IER &= ~bitmask;
74 H8300_GPIO_FREE(H8300_GPIO_P8, bitmask);
75 break ;
76 case EXT_IRQ4:
77 case EXT_IRQ5:
78 *(volatile unsigned char *)IER &= ~bitmask;
79 H8300_GPIO_FREE(H8300_GPIO_P9, bitmask);
80 break;