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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / mips / kernel / cpu-probe.c
blob0bab464b8e33be322e64dacc1263189c71dbb1ac
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/elf.h>
28 #include <asm/spram.h>
29 #include <asm/uaccess.h>
30
31 /*
32 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
33 * the implementation of the "wait" feature differs between CPU families. This
34 * points to the function that implements CPU specific wait.
35 * The wait instruction stops the pipeline and reduces the power consumption of
36 * the CPU very much.
37 */
38 void (*cpu_wait)(void);
39 EXPORT_SYMBOL(cpu_wait);
40
41 static void r3081_wait(void)
42 {
43 unsigned long cfg = read_c0_conf();
44 write_c0_conf(cfg | R30XX_CONF_HALT);
45 }
46
47 static void r39xx_wait(void)
48 {
49 local_irq_disable();
50 if (!need_resched())
51 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
52 local_irq_enable();
53 }
54
55 extern void r4k_wait(void);
56
57 /*
58 * This variant is preferable as it allows testing need_resched and going to
59 * sleep depending on the outcome atomically. Unfortunately the "It is
60 * implementation-dependent whether the pipeline restarts when a non-enabled
61 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
62 * using this version a gamble.
63 */
64 void r4k_wait_irqoff(void)
65 {
66 local_irq_disable();
67 if (!need_resched())
68 __asm__(" .set push \n"
69 " .set mips3 \n"
70 " wait \n"
71 " .set pop \n");
72 local_irq_enable();
73 __asm__(" .globl __pastwait \n"
74 "__pastwait: \n");
75 }
76
77 /*
78 * The RM7000 variant has to handle erratum 38. The workaround is to not
79 * have any pending stores when the WAIT instruction is executed.
80 */
81 static void rm7k_wait_irqoff(void)
82 {
83 local_irq_disable();
84 if (!need_resched())
85 __asm__(
86 " .set push \n"
87 " .set mips3 \n"
88 " .set noat \n"
89 " mfc0 $1, $12 \n"
90 " sync \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
92 " wait \n"
93 " mtc0 $1, $12 # stalls until W stage \n"
94 " .set pop \n");
95 local_irq_enable();
96 }
97
98 /*
99 * The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter.
101 * alchemy/common/time.c may override cpu_wait!
102 */
103 static void au1k_wait(void)
104 {
105 __asm__(" .set mips3 \n"
106 " cache 0x14, 0(%0) \n"
107 " cache 0x14, 32(%0) \n"
108 " sync \n"
109 " nop \n"
110 " wait \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " nop \n"
115 " .set mips0 \n"
116 : : "r" (au1k_wait));
117 }
118
119 static int __initdata nowait;
120
121 static int __init wait_disable(char *s)
122 {
123 nowait = 1;
124
125 return 1;
126 }
127
128 __setup("nowait", wait_disable);
129
130 static int __cpuinitdata mips_fpu_disabled;
131
132 static int __init fpu_disable(char *s)
133 {
134 cpu_data[0].options &= ~MIPS_CPU_FPU;
135 mips_fpu_disabled = 1;
136
137 return 1;
138 }
139
140 __setup("nofpu", fpu_disable);
141
142 int __cpuinitdata mips_dsp_disabled;
143
144 static int __init dsp_disable(char *s)
145 {
146 cpu_data[0].ases &= ~MIPS_ASE_DSP;
147 mips_dsp_disabled = 1;
148
149 return 1;
150 }
151
152 __setup("nodsp", dsp_disable);
153
154 void __init check_wait(void)
155 {
156 struct cpuinfo_mips *c = &current_cpu_data;
157
158 if (nowait) {
159 printk("Wait instruction disabled.\n");
160 return;
161 }
162
163 switch (c->cputype) {
164 case CPU_R3081:
165 case CPU_R3081E:
166 cpu_wait = r3081_wait;
167 break;
168 case CPU_TX3927:
169 cpu_wait = r39xx_wait;
170 break;
171 case CPU_R4200:
172 /* case CPU_R4300: */
173 case CPU_R4600:
174 case CPU_R4640:
175 case CPU_R4650:
176 case CPU_R4700:
177 case CPU_R5000:
178 case CPU_R5500:
179 case CPU_NEVADA:
180 case CPU_4KC:
181 case CPU_4KEC:
182 case CPU_4KSC:
183 case CPU_5KC:
184 case CPU_25KF:
185 case CPU_PR4450:
186 case CPU_BMIPS3300:
187 case CPU_BMIPS4350:
188 case CPU_BMIPS4380:
189 case CPU_BMIPS5000:
190 case CPU_CAVIUM_OCTEON:
191 case CPU_CAVIUM_OCTEON_PLUS:
192 case CPU_CAVIUM_OCTEON2:
193 case CPU_JZRISC:
194 case CPU_XLR:
195 case CPU_XLP:
196 cpu_wait = r4k_wait;
197 break;
198
199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;
202
203 case CPU_24K:
204 case CPU_34K:
205 case CPU_1004K:
206 cpu_wait = r4k_wait;
207 if (read_c0_config7() & MIPS_CONF7_WII)
208 cpu_wait = r4k_wait_irqoff;
209 break;
210
211 case CPU_74K:
212 cpu_wait = r4k_wait;
213 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
214 cpu_wait = r4k_wait_irqoff;
215 break;
216
217 case CPU_TX49XX:
218 cpu_wait = r4k_wait_irqoff;
219 break;
220 case CPU_ALCHEMY:
221 cpu_wait = au1k_wait;
222 break;
223 case CPU_20KC:
224 /*
225 * WAIT on Rev1.0 has E1, E2, E3 and E16.
226 * WAIT on Rev2.0 and Rev3.0 has E16.
227 * Rev3.1 WAIT is nop, why bother
228 */
229 if ((c->processor_id & 0xff) <= 0x64)
230 break;
231
232 /*
233 * Another rev is incremeting c0_count at a reduced clock
234 * rate while in WAIT mode. So we basically have the choice
235 * between using the cp0 timer as clocksource or avoiding
236 * the WAIT instruction. Until more details are known,
237 * disable the use of WAIT for 20Kc entirely.
238 cpu_wait = r4k_wait;
239 */
240 break;
241 case CPU_RM9000:
242 if ((c->processor_id & 0x00ff) >= 0x40)
243 cpu_wait = r4k_wait;
244 break;
245 default:
246 break;
247 }
248 }
249
250 static inline void check_errata(void)
251 {
252 struct cpuinfo_mips *c = &current_cpu_data;
253
254 switch (c->cputype) {
255 case CPU_34K:
256 /*
257 * Erratum "RPS May Cause Incorrect Instruction Execution"
258 * This code only handles VPE0, any SMP/SMTC/RTOS code
259 * making use of VPE1 will be responsable for that VPE.
260 */
261 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
262 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
263 break;
264 default:
265 break;
266 }
267 }
268
269 void __init check_bugs32(void)
270 {
271 check_errata();
272 }
273
274 /*
275 * Probe whether cpu has config register by trying to play with
276 * alternate cache bit and see whether it matters.
277 * It's used by cpu_probe to distinguish between R3000A and R3081.
278 */
279 static inline int cpu_has_confreg(void)
280 {
281 #ifdef CONFIG_CPU_R3000
282 extern unsigned long r3k_cache_size(unsigned long);
283 unsigned long size1, size2;
284 unsigned long cfg = read_c0_conf();
285
286 size1 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg ^ R30XX_CONF_AC);
288 size2 = r3k_cache_size(ST0_ISC);
289 write_c0_conf(cfg);
290 return size1 != size2;
291 #else
292 return 0;
293 #endif
294 }
295
296 static inline void set_elf_platform(int cpu, const char *plat)
297 {
298 if (cpu == 0)
299 __elf_platform = plat;
300 }
301
302 /*
303 * Get the FPU Implementation/Revision.
304 */
305 static inline unsigned long cpu_get_fpu_id(void)
306 {
307 unsigned long tmp, fpu_id;
308
309 tmp = read_c0_status();
310 __enable_fpu();
311 fpu_id = read_32bit_cp1_register(CP1_REVISION);
312 write_c0_status(tmp);
313 return fpu_id;
314 }
315
316 /*
317 * Check the CPU has an FPU the official way.
318 */
319 static inline int __cpu_has_fpu(void)
320 {
321 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
322 }
323
324 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
325 {
326 #ifdef __NEED_VMBITS_PROBE
327 write_c0_entryhi(0x3fffffffffffe000ULL);
328 back_to_back_c0_hazard();
329 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
330 #endif
331 }
332
333 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
334 | MIPS_CPU_COUNTER)
335
336 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
337 {
338 switch (c->processor_id & 0xff00) {
339 case PRID_IMP_R2000:
340 c->cputype = CPU_R2000;
341 __cpu_name[cpu] = "R2000";
342 c->isa_level = MIPS_CPU_ISA_I;
343 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
344 MIPS_CPU_NOFPUEX;
345 if (__cpu_has_fpu())
346 c->options |= MIPS_CPU_FPU;
347 c->tlbsize = 64;
348 break;
349 case PRID_IMP_R3000:
350 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
351 if (cpu_has_confreg()) {
352 c->cputype = CPU_R3081E;
353 __cpu_name[cpu] = "R3081";
354 } else {
355 c->cputype = CPU_R3000A;
356 __cpu_name[cpu] = "R3000A";
357 }
358 break;
359 } else {
360 c->cputype = CPU_R3000;
361 __cpu_name[cpu] = "R3000";
362 }
363 c->isa_level = MIPS_CPU_ISA_I;
364 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
365 MIPS_CPU_NOFPUEX;
366 if (__cpu_has_fpu())
367 c->options |= MIPS_CPU_FPU;
368 c->tlbsize = 64;
369 break;
370 case PRID_IMP_R4000:
371 if (read_c0_config() & CONF_SC) {
372 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
373 c->cputype = CPU_R4400PC;
374 __cpu_name[cpu] = "R4400PC";
375 } else {
376 c->cputype = CPU_R4000PC;
377 __cpu_name[cpu] = "R4000PC";
378 }
379 } else {
380 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
381 c->cputype = CPU_R4400SC;
382 __cpu_name[cpu] = "R4400SC";
383 } else {
384 c->cputype = CPU_R4000SC;
385 __cpu_name[cpu] = "R4000SC";
386 }
387 }
388
389 c->isa_level = MIPS_CPU_ISA_III;
390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
391 MIPS_CPU_WATCH | MIPS_CPU_VCE |
392 MIPS_CPU_LLSC;
393 c->tlbsize = 48;
394 break;
395 case PRID_IMP_VR41XX:
396 switch (c->processor_id & 0xf0) {
397 case PRID_REV_VR4111:
398 c->cputype = CPU_VR4111;
399 __cpu_name[cpu] = "NEC VR4111";
400 break;
401 case PRID_REV_VR4121:
402 c->cputype = CPU_VR4121;
403 __cpu_name[cpu] = "NEC VR4121";
404 break;
405 case PRID_REV_VR4122:
406 if ((c->processor_id & 0xf) < 0x3) {
407 c->cputype = CPU_VR4122;
408 __cpu_name[cpu] = "NEC VR4122";
409 } else {
410 c->cputype = CPU_VR4181A;
411 __cpu_name[cpu] = "NEC VR4181A";
412 }
413 break;
414 case PRID_REV_VR4130:
415 if ((c->processor_id & 0xf) < 0x4) {
416 c->cputype = CPU_VR4131;
417 __cpu_name[cpu] = "NEC VR4131";
418 } else {
419 c->cputype = CPU_VR4133;
420 __cpu_name[cpu] = "NEC VR4133";
421 }
422 break;
423 default:
424 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
425 c->cputype = CPU_VR41XX;
426 __cpu_name[cpu] = "NEC Vr41xx";
427 break;
428 }
429 c->isa_level = MIPS_CPU_ISA_III;
430 c->options = R4K_OPTS;
431 c->tlbsize = 32;
432 break;
433 case PRID_IMP_R4300:
434 c->cputype = CPU_R4300;
435 __cpu_name[cpu] = "R4300";
436 c->isa_level = MIPS_CPU_ISA_III;
437 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
438 MIPS_CPU_LLSC;
439 c->tlbsize = 32;
440 break;
441 case PRID_IMP_R4600:
442 c->cputype = CPU_R4600;
443 __cpu_name[cpu] = "R4600";
444 c->isa_level = MIPS_CPU_ISA_III;
445 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
446 MIPS_CPU_LLSC;
447 c->tlbsize = 48;
448 break;
449 #if 0
450 case PRID_IMP_R4650:
451 /*
452 * This processor doesn't have an MMU, so it's not
453 * "real easy" to run Linux on it. It is left purely
454 * for documentation. Commented out because it shares
455 * it's c0_prid id number with the TX3900.
456 */
457 c->cputype = CPU_R4650;
458 __cpu_name[cpu] = "R4650";
459 c->isa_level = MIPS_CPU_ISA_III;
460 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
461 c->tlbsize = 48;
462 break;
463 #endif
464 case PRID_IMP_TX39:
465 c->isa_level = MIPS_CPU_ISA_I;
466 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
467
468 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
469 c->cputype = CPU_TX3927;
470 __cpu_name[cpu] = "TX3927";
471 c->tlbsize = 64;
472 } else {
473 switch (c->processor_id & 0xff) {
474 case PRID_REV_TX3912:
475 c->cputype = CPU_TX3912;
476 __cpu_name[cpu] = "TX3912";
477 c->tlbsize = 32;
478 break;
479 case PRID_REV_TX3922:
480 c->cputype = CPU_TX3922;
481 __cpu_name[cpu] = "TX3922";
482 c->tlbsize = 64;
483 break;
484 }
485 }
486 break;
487 case PRID_IMP_R4700:
488 c->cputype = CPU_R4700;
489 __cpu_name[cpu] = "R4700";
490 c->isa_level = MIPS_CPU_ISA_III;
491 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
492 MIPS_CPU_LLSC;
493 c->tlbsize = 48;
494 break;
495 case PRID_IMP_TX49:
496 c->cputype = CPU_TX49XX;
497 __cpu_name[cpu] = "R49XX";
498 c->isa_level = MIPS_CPU_ISA_III;
499 c->options = R4K_OPTS | MIPS_CPU_LLSC;
500 if (!(c->processor_id & 0x08))
501 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
502 c->tlbsize = 48;
503 break;
504 case PRID_IMP_R5000:
505 c->cputype = CPU_R5000;
506 __cpu_name[cpu] = "R5000";
507 c->isa_level = MIPS_CPU_ISA_IV;
508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
509 MIPS_CPU_LLSC;
510 c->tlbsize = 48;
511 break;
512 case PRID_IMP_R5432:
513 c->cputype = CPU_R5432;
514 __cpu_name[cpu] = "R5432";
515 c->isa_level = MIPS_CPU_ISA_IV;
516 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
517 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
518 c->tlbsize = 48;
519 break;
520 case PRID_IMP_R5500:
521 c->cputype = CPU_R5500;
522 __cpu_name[cpu] = "R5500";
523 c->isa_level = MIPS_CPU_ISA_IV;
524 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
525 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
526 c->tlbsize = 48;
527 break;
528 case PRID_IMP_NEVADA:
529 c->cputype = CPU_NEVADA;
530 __cpu_name[cpu] = "Nevada";
531 c->isa_level = MIPS_CPU_ISA_IV;
532 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
533 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
534 c->tlbsize = 48;
535 break;
536 case PRID_IMP_R6000:
537 c->cputype = CPU_R6000;
538 __cpu_name[cpu] = "R6000";
539 c->isa_level = MIPS_CPU_ISA_II;
540 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
541 MIPS_CPU_LLSC;
542 c->tlbsize = 32;
543 break;
544 case PRID_IMP_R6000A:
545 c->cputype = CPU_R6000A;
546 __cpu_name[cpu] = "R6000A";
547 c->isa_level = MIPS_CPU_ISA_II;
548 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
549 MIPS_CPU_LLSC;
550 c->tlbsize = 32;
551 break;
552 case PRID_IMP_RM7000:
553 c->cputype = CPU_RM7000;
554 __cpu_name[cpu] = "RM7000";
555 c->isa_level = MIPS_CPU_ISA_IV;
556 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
557 MIPS_CPU_LLSC;
558 /*
559 * Undocumented RM7000: Bit 29 in the info register of
560 * the RM7000 v2.0 indicates if the TLB has 48 or 64
561 * entries.
562 *
563 * 29 1 => 64 entry JTLB
564 * 0 => 48 entry JTLB
565 */
566 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
567 break;
568 case PRID_IMP_RM9000:
569 c->cputype = CPU_RM9000;
570 __cpu_name[cpu] = "RM9000";
571 c->isa_level = MIPS_CPU_ISA_IV;
572 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
573 MIPS_CPU_LLSC;
574 /*
575 * Bit 29 in the info register of the RM9000
576 * indicates if the TLB has 48 or 64 entries.
577 *
578 * 29 1 => 64 entry JTLB
579 * 0 => 48 entry JTLB
580 */
581 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
582 break;
583 case PRID_IMP_R8000:
584 c->cputype = CPU_R8000;
585 __cpu_name[cpu] = "RM8000";
586 c->isa_level = MIPS_CPU_ISA_IV;
587 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
588 MIPS_CPU_FPU | MIPS_CPU_32FPR |
589 MIPS_CPU_LLSC;
590 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
591 break;
592 case PRID_IMP_R10000:
593 c->cputype = CPU_R10000;
594 __cpu_name[cpu] = "R10000";
595 c->isa_level = MIPS_CPU_ISA_IV;
596 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
597 MIPS_CPU_FPU | MIPS_CPU_32FPR |
598 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
599 MIPS_CPU_LLSC;
600 c->tlbsize = 64;
601 break;
602 case PRID_IMP_R12000:
603 c->cputype = CPU_R12000;
604 __cpu_name[cpu] = "R12000";
605 c->isa_level = MIPS_CPU_ISA_IV;
606 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
607 MIPS_CPU_FPU | MIPS_CPU_32FPR |
608 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
609 MIPS_CPU_LLSC;
610 c->tlbsize = 64;
611 break;
612 case PRID_IMP_R14000:
613 c->cputype = CPU_R14000;
614 __cpu_name[cpu] = "R14000";
615 c->isa_level = MIPS_CPU_ISA_IV;
616 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
617 MIPS_CPU_FPU | MIPS_CPU_32FPR |
618 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
619 MIPS_CPU_LLSC;
620 c->tlbsize = 64;
621 break;
622 case PRID_IMP_LOONGSON2:
623 c->cputype = CPU_LOONGSON2;
624 __cpu_name[cpu] = "ICT Loongson-2";
625
626 switch (c->processor_id & PRID_REV_MASK) {
627 case PRID_REV_LOONGSON2E:
628 set_elf_platform(cpu, "loongson2e");
629 break;
630 case PRID_REV_LOONGSON2F:
631 set_elf_platform(cpu, "loongson2f");
632 break;
633 }
634
635 c->isa_level = MIPS_CPU_ISA_III;
636 c->options = R4K_OPTS |
637 MIPS_CPU_FPU | MIPS_CPU_LLSC |
638 MIPS_CPU_32FPR;
639 c->tlbsize = 64;
640 break;
641 }
642 }
643
644 static char unknown_isa[] __cpuinitdata = KERN_ERR \
645 "Unsupported ISA type, c0.config0: %d.";
646
647 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
648 {
649 unsigned int config0;
650 int isa;
651
652 config0 = read_c0_config();
653
654 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
655 c->options |= MIPS_CPU_TLB;
656 isa = (config0 & MIPS_CONF_AT) >> 13;
657 switch (isa) {
658 case 0:
659 switch ((config0 & MIPS_CONF_AR) >> 10) {
660 case 0:
661 c->isa_level = MIPS_CPU_ISA_M32R1;
662 break;
663 case 1:
664 c->isa_level = MIPS_CPU_ISA_M32R2;
665 break;
666 default:
667 goto unknown;
668 }
669 break;
670 case 2:
671 switch ((config0 & MIPS_CONF_AR) >> 10) {
672 case 0:
673 c->isa_level = MIPS_CPU_ISA_M64R1;
674 break;
675 case 1:
676 c->isa_level = MIPS_CPU_ISA_M64R2;
677 break;
678 default:
679 goto unknown;
680 }
681 break;
682 default:
683 goto unknown;
684 }
685
686 return config0 & MIPS_CONF_M;
687
688 unknown:
689 panic(unknown_isa, config0);
690 }
691
692 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
693 {
694 unsigned int config1;
695
696 config1 = read_c0_config1();
697
698 if (config1 & MIPS_CONF1_MD)
699 c->ases |= MIPS_ASE_MDMX;
700 if (config1 & MIPS_CONF1_WR)
701 c->options |= MIPS_CPU_WATCH;
702 if (config1 & MIPS_CONF1_CA)
703 c->ases |= MIPS_ASE_MIPS16;
704 if (config1 & MIPS_CONF1_EP)
705 c->options |= MIPS_CPU_EJTAG;
706 if (config1 & MIPS_CONF1_FP) {
707 c->options |= MIPS_CPU_FPU;
708 c->options |= MIPS_CPU_32FPR;
709 }
710 if (cpu_has_tlb)
711 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
712
713 return config1 & MIPS_CONF_M;
714 }
715
716 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
717 {
718 unsigned int config2;
719
720 config2 = read_c0_config2();
721
722 if (config2 & MIPS_CONF2_SL)
723 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
724
725 return config2 & MIPS_CONF_M;
726 }
727
728 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
729 {
730 unsigned int config3;
731
732 config3 = read_c0_config3();
733
734 if (config3 & MIPS_CONF3_SM)
735 c->ases |= MIPS_ASE_SMARTMIPS;
736 if (config3 & MIPS_CONF3_DSP)
737 c->ases |= MIPS_ASE_DSP;
738 if (config3 & MIPS_CONF3_VINT)
739 c->options |= MIPS_CPU_VINT;
740 if (config3 & MIPS_CONF3_VEIC)
741 c->options |= MIPS_CPU_VEIC;
742 if (config3 & MIPS_CONF3_MT)
743 c->ases |= MIPS_ASE_MIPSMT;
744 if (config3 & MIPS_CONF3_ULRI)
745 c->options |= MIPS_CPU_ULRI;
746
747 return config3 & MIPS_CONF_M;
748 }
749
750 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
751 {
752 unsigned int config4;
753
754 config4 = read_c0_config4();
755
756 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
757 && cpu_has_tlb)
758 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
759
760 c->kscratch_mask = (config4 >> 16) & 0xff;
761
762 return config4 & MIPS_CONF_M;
763 }
764
765 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
766 {
767 int ok;
768
769 /* MIPS32 or MIPS64 compliant CPU. */
770 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
771 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
772
773 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
774
775 ok = decode_config0(c); /* Read Config registers. */
776 BUG_ON(!ok); /* Arch spec violation! */
777 if (ok)
778 ok = decode_config1(c);
779 if (ok)
780 ok = decode_config2(c);
781 if (ok)
782 ok = decode_config3(c);
783 if (ok)
784 ok = decode_config4(c);
785
786 mips_probe_watch_registers(c);
787
788 if (cpu_has_mips_r2)
789 c->core = read_c0_ebase() & 0x3ff;
790 }
791
792 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
793 {
794 decode_configs(c);
795 switch (c->processor_id & 0xff00) {
796 case PRID_IMP_4KC:
797 c->cputype = CPU_4KC;
798 __cpu_name[cpu] = "MIPS 4Kc";
799 break;
800 case PRID_IMP_4KEC:
801 case PRID_IMP_4KECR2:
802 c->cputype = CPU_4KEC;
803 __cpu_name[cpu] = "MIPS 4KEc";
804 break;
805 case PRID_IMP_4KSC:
806 case PRID_IMP_4KSD:
807 c->cputype = CPU_4KSC;
808 __cpu_name[cpu] = "MIPS 4KSc";
809 break;
810 case PRID_IMP_5KC:
811 c->cputype = CPU_5KC;
812 __cpu_name[cpu] = "MIPS 5Kc";
813 break;
814 case PRID_IMP_20KC:
815 c->cputype = CPU_20KC;
816 __cpu_name[cpu] = "MIPS 20Kc";
817 break;
818 case PRID_IMP_24K:
819 case PRID_IMP_24KE:
820 c->cputype = CPU_24K;
821 __cpu_name[cpu] = "MIPS 24Kc";
822 break;
823 case PRID_IMP_25KF:
824 c->cputype = CPU_25KF;
825 __cpu_name[cpu] = "MIPS 25Kc";
826 break;
827 case PRID_IMP_34K:
828 c->cputype = CPU_34K;
829 __cpu_name[cpu] = "MIPS 34Kc";
830 break;
831 case PRID_IMP_74K:
832 c->cputype = CPU_74K;
833 __cpu_name[cpu] = "MIPS 74Kc";
834 break;
835 case PRID_IMP_1004K:
836 c->cputype = CPU_1004K;
837 __cpu_name[cpu] = "MIPS 1004Kc";
838 break;
839 }
840
841 spram_config();
842 }
843
844 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
845 {
846 decode_configs(c);
847 switch (c->processor_id & 0xff00) {
848 case PRID_IMP_AU1_REV1:
849 case PRID_IMP_AU1_REV2:
850 c->cputype = CPU_ALCHEMY;
851 switch ((c->processor_id >> 24) & 0xff) {
852 case 0:
853 __cpu_name[cpu] = "Au1000";
854 break;
855 case 1:
856 __cpu_name[cpu] = "Au1500";
857 break;
858 case 2:
859 __cpu_name[cpu] = "Au1100";
860 break;
861 case 3:
862 __cpu_name[cpu] = "Au1550";
863 break;
864 case 4:
865 __cpu_name[cpu] = "Au1200";
866 if ((c->processor_id & 0xff) == 2)
867 __cpu_name[cpu] = "Au1250";
868 break;
869 case 5:
870 __cpu_name[cpu] = "Au1210";
871 break;
872 default:
873 __cpu_name[cpu] = "Au1xxx";
874 break;
875 }
876 break;
877 }
878 }
879
880 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
881 {
882 decode_configs(c);
883
884 switch (c->processor_id & 0xff00) {
885 case PRID_IMP_SB1:
886 c->cputype = CPU_SB1;
887 __cpu_name[cpu] = "SiByte SB1";
888 /* FPU in pass1 is known to have issues. */
889 if ((c->processor_id & 0xff) < 0x02)
890 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
891 break;
892 case PRID_IMP_SB1A:
893 c->cputype = CPU_SB1A;
894 __cpu_name[cpu] = "SiByte SB1A";
895 break;
896 }
897 }
898
899 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
900 {
901 decode_configs(c);
902 switch (c->processor_id & 0xff00) {
903 case PRID_IMP_SR71000:
904 c->cputype = CPU_SR71000;
905 __cpu_name[cpu] = "Sandcraft SR71000";
906 c->scache.ways = 8;
907 c->tlbsize = 64;
908 break;
909 }
910 }
911
912 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
913 {
914 decode_configs(c);
915 switch (c->processor_id & 0xff00) {
916 case PRID_IMP_PR4450:
917 c->cputype = CPU_PR4450;
918 __cpu_name[cpu] = "Philips PR4450";
919 c->isa_level = MIPS_CPU_ISA_M32R1;
920 break;
921 }
922 }
923
924 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
925 {
926 decode_configs(c);
927 switch (c->processor_id & 0xff00) {
928 case PRID_IMP_BMIPS32_REV4:
929 case PRID_IMP_BMIPS32_REV8:
930 c->cputype = CPU_BMIPS32;
931 __cpu_name[cpu] = "Broadcom BMIPS32";
932 set_elf_platform(cpu, "bmips32");
933 break;
934 case PRID_IMP_BMIPS3300:
935 case PRID_IMP_BMIPS3300_ALT:
936 case PRID_IMP_BMIPS3300_BUG:
937 c->cputype = CPU_BMIPS3300;
938 __cpu_name[cpu] = "Broadcom BMIPS3300";
939 set_elf_platform(cpu, "bmips3300");
940 break;
941 case PRID_IMP_BMIPS43XX: {
942 int rev = c->processor_id & 0xff;
943
944 if (rev >= PRID_REV_BMIPS4380_LO &&
945 rev <= PRID_REV_BMIPS4380_HI) {
946 c->cputype = CPU_BMIPS4380;
947 __cpu_name[cpu] = "Broadcom BMIPS4380";
948 set_elf_platform(cpu, "bmips4380");
949 } else {
950 c->cputype = CPU_BMIPS4350;
951 __cpu_name[cpu] = "Broadcom BMIPS4350";
952 set_elf_platform(cpu, "bmips4350");
953 }
954 break;
955 }
956 case PRID_IMP_BMIPS5000:
957 c->cputype = CPU_BMIPS5000;
958 __cpu_name[cpu] = "Broadcom BMIPS5000";
959 set_elf_platform(cpu, "bmips5000");
960 c->options |= MIPS_CPU_ULRI;
961 break;
962 }
963 }
964
965 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
966 {
967 decode_configs(c);
968 switch (c->processor_id & 0xff00) {
969 case PRID_IMP_CAVIUM_CN38XX:
970 case PRID_IMP_CAVIUM_CN31XX:
971 case PRID_IMP_CAVIUM_CN30XX:
972 c->cputype = CPU_CAVIUM_OCTEON;
973 __cpu_name[cpu] = "Cavium Octeon";
974 goto platform;
975 case PRID_IMP_CAVIUM_CN58XX:
976 case PRID_IMP_CAVIUM_CN56XX:
977 case PRID_IMP_CAVIUM_CN50XX:
978 case PRID_IMP_CAVIUM_CN52XX:
979 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
980 __cpu_name[cpu] = "Cavium Octeon+";
981 platform:
982 set_elf_platform(cpu, "octeon");
983 break;
984 case PRID_IMP_CAVIUM_CN61XX:
985 case PRID_IMP_CAVIUM_CN63XX:
986 case PRID_IMP_CAVIUM_CN66XX:
987 case PRID_IMP_CAVIUM_CN68XX:
988 c->cputype = CPU_CAVIUM_OCTEON2;
989 __cpu_name[cpu] = "Cavium Octeon II";
990 set_elf_platform(cpu, "octeon2");
991 break;
992 default:
993 printk(KERN_INFO "Unknown Octeon chip!\n");
994 c->cputype = CPU_UNKNOWN;
995 break;
996 }
997 }
998
999 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1000 {
1001 decode_configs(c);
1002 /* JZRISC does not implement the CP0 counter. */
1003 c->options &= ~MIPS_CPU_COUNTER;
1004 switch (c->processor_id & 0xff00) {
1005 case PRID_IMP_JZRISC:
1006 c->cputype = CPU_JZRISC;
1007 __cpu_name[cpu] = "Ingenic JZRISC";
1008 break;
1009 default:
1010 panic("Unknown Ingenic Processor ID!");
1011 break;
1012 }
1013 }
1014
1015 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1016 {
1017 decode_configs(c);
1018
1019 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1020 c->cputype = CPU_ALCHEMY;
1021 __cpu_name[cpu] = "Au1300";
1022 /* following stuff is not for Alchemy */
1023 return;
1024 }
1025
1026 c->options = (MIPS_CPU_TLB |
1027 MIPS_CPU_4KEX |
1028 MIPS_CPU_COUNTER |
1029 MIPS_CPU_DIVEC |
1030 MIPS_CPU_WATCH |
1031 MIPS_CPU_EJTAG |
1032 MIPS_CPU_LLSC);
1033
1034 switch (c->processor_id & 0xff00) {
1035 case PRID_IMP_NETLOGIC_XLP8XX:
1036 case PRID_IMP_NETLOGIC_XLP3XX:
1037 c->cputype = CPU_XLP;
1038 __cpu_name[cpu] = "Netlogic XLP";
1039 break;
1040
1041 case PRID_IMP_NETLOGIC_XLR732:
1042 case PRID_IMP_NETLOGIC_XLR716:
1043 case PRID_IMP_NETLOGIC_XLR532:
1044 case PRID_IMP_NETLOGIC_XLR308:
1045 case PRID_IMP_NETLOGIC_XLR532C:
1046 case PRID_IMP_NETLOGIC_XLR516C:
1047 case PRID_IMP_NETLOGIC_XLR508C:
1048 case PRID_IMP_NETLOGIC_XLR308C:
1049 c->cputype = CPU_XLR;
1050 __cpu_name[cpu] = "Netlogic XLR";
1051 break;
1052
1053 case PRID_IMP_NETLOGIC_XLS608:
1054 case PRID_IMP_NETLOGIC_XLS408:
1055 case PRID_IMP_NETLOGIC_XLS404:
1056 case PRID_IMP_NETLOGIC_XLS208:
1057 case PRID_IMP_NETLOGIC_XLS204:
1058 case PRID_IMP_NETLOGIC_XLS108:
1059 case PRID_IMP_NETLOGIC_XLS104:
1060 case PRID_IMP_NETLOGIC_XLS616B:
1061 case PRID_IMP_NETLOGIC_XLS608B:
1062 case PRID_IMP_NETLOGIC_XLS416B:
1063 case PRID_IMP_NETLOGIC_XLS412B:
1064 case PRID_IMP_NETLOGIC_XLS408B:
1065 case PRID_IMP_NETLOGIC_XLS404B:
1066 c->cputype = CPU_XLR;
1067 __cpu_name[cpu] = "Netlogic XLS";
1068 break;
1069
1070 default:
1071 pr_info("Unknown Netlogic chip id [%02x]!\n",
1072 c->processor_id);
1073 c->cputype = CPU_XLR;
1074 break;
1075 }
1076
1077 if (c->cputype == CPU_XLP) {
1078 c->isa_level = MIPS_CPU_ISA_M64R2;
1079 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1080 /* This will be updated again after all threads are woken up */
1081 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1082 } else {
1083 c->isa_level = MIPS_CPU_ISA_M64R1;
1084 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1085 }
1086 }
1087
1088 #ifdef CONFIG_64BIT
1089 /* For use by uaccess.h */
1090 u64 __ua_limit;
1091 EXPORT_SYMBOL(__ua_limit);
1092 #endif
1093
1094 const char *__cpu_name[NR_CPUS];
1095 const char *__elf_platform;
1096
1097 __cpuinit void cpu_probe(void)
1098 {
1099 struct cpuinfo_mips *c = &current_cpu_data;
1100 unsigned int cpu = smp_processor_id();
1101
1102 c->processor_id = PRID_IMP_UNKNOWN;
1103 c->fpu_id = FPIR_IMP_NONE;
1104 c->cputype = CPU_UNKNOWN;
1105
1106 c->processor_id = read_c0_prid();
1107 switch (c->processor_id & 0xff0000) {
1108 case PRID_COMP_LEGACY:
1109 cpu_probe_legacy(c, cpu);
1110 break;
1111 case PRID_COMP_MIPS:
1112 cpu_probe_mips(c, cpu);
1113 break;
1114 case PRID_COMP_ALCHEMY:
1115 cpu_probe_alchemy(c, cpu);
1116 break;
1117 case PRID_COMP_SIBYTE:
1118 cpu_probe_sibyte(c, cpu);
1119 break;
1120 case PRID_COMP_BROADCOM:
1121 cpu_probe_broadcom(c, cpu);
1122 break;
1123 case PRID_COMP_SANDCRAFT:
1124 cpu_probe_sandcraft(c, cpu);
1125 break;
1126 case PRID_COMP_NXP:
1127 cpu_probe_nxp(c, cpu);
1128 break;
1129 case PRID_COMP_CAVIUM:
1130 cpu_probe_cavium(c, cpu);
1131 break;
1132 case PRID_COMP_INGENIC:
1133 cpu_probe_ingenic(c, cpu);
1134 break;
1135 case PRID_COMP_NETLOGIC:
1136 cpu_probe_netlogic(c, cpu);
1137 break;
1138 }
1139
1140 BUG_ON(!__cpu_name[cpu]);
1141 BUG_ON(c->cputype == CPU_UNKNOWN);
1142
1143 /*
1144 * Platform code can force the cpu type to optimize code
1145 * generation. In that case be sure the cpu type is correctly
1146 * manually setup otherwise it could trigger some nasty bugs.
1147 */
1148 BUG_ON(current_cpu_type() != c->cputype);
1149
1150 if (mips_fpu_disabled)
1151 c->options &= ~MIPS_CPU_FPU;
1152
1153 if (mips_dsp_disabled)
1154 c->ases &= ~MIPS_ASE_DSP;
1155
1156 if (c->options & MIPS_CPU_FPU) {
1157 c->fpu_id = cpu_get_fpu_id();
1158
1159 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1160 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1161 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1162 c->isa_level == MIPS_CPU_ISA_M64R2) {
1163 if (c->fpu_id & MIPS_FPIR_3D)
1164 c->ases |= MIPS_ASE_MIPS3D;
1165 }
1166 }
1167
1168 if (cpu_has_mips_r2)
1169 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1170 else
1171 c->srsets = 1;
1172
1173 cpu_probe_vmbits(c);
1174
1175 #ifdef CONFIG_64BIT
1176 if (cpu == 0)
1177 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1178 #endif
1179 }
1180
1181 __cpuinit void cpu_report(void)
1182 {
1183 struct cpuinfo_mips *c = &current_cpu_data;
1184
1185 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1186 c->processor_id, cpu_name_string());
1187 if (c->options & MIPS_CPU_FPU)
1188 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1189 }