spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / mips / kernel / csrc-r4k.c
blobdecd1fa38d551bf132f9bba4aa2a48400e129ac8
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8 #include <linux/clocksource.h>
9 #include <linux/init.h>
11 #include <asm/time.h>
13 static cycle_t c0_hpt_read(struct clocksource *cs)
15 return read_c0_count();
18 static struct clocksource clocksource_mips = {
19 .name = "MIPS",
20 .read = c0_hpt_read,
21 .mask = CLOCKSOURCE_MASK(32),
22 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
25 int __init init_r4k_clocksource(void)
27 if (!cpu_has_counter || !mips_hpt_frequency)
28 return -ENXIO;
30 /* Calculate a somewhat reasonable rating value */
31 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
33 clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
35 return 0;