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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / mips / kernel / traps.c
blobd79ae5437b5871efda13f052c5f7511ccf9587b9
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/kprobes.h>
29 #include <linux/notifier.h>
30 #include <linux/kdb.h>
31 #include <linux/irq.h>
32 #include <linux/perf_event.h>
33
34 #include <asm/bootinfo.h>
35 #include <asm/branch.h>
36 #include <asm/break.h>
37 #include <asm/cop2.h>
38 #include <asm/cpu.h>
39 #include <asm/dsp.h>
40 #include <asm/fpu.h>
41 #include <asm/fpu_emulator.h>
42 #include <asm/mipsregs.h>
43 #include <asm/mipsmtregs.h>
44 #include <asm/module.h>
45 #include <asm/pgtable.h>
46 #include <asm/ptrace.h>
47 #include <asm/sections.h>
48 #include <asm/system.h>
49 #include <asm/tlbdebug.h>
50 #include <asm/traps.h>
51 #include <asm/uaccess.h>
52 #include <asm/watch.h>
53 #include <asm/mmu_context.h>
54 #include <asm/types.h>
55 #include <asm/stacktrace.h>
56 #include <asm/uasm.h>
57
58 extern void check_wait(void);
59 extern asmlinkage void r4k_wait(void);
60 extern asmlinkage void rollback_handle_int(void);
61 extern asmlinkage void handle_int(void);
62 extern asmlinkage void handle_tlbm(void);
63 extern asmlinkage void handle_tlbl(void);
64 extern asmlinkage void handle_tlbs(void);
65 extern asmlinkage void handle_adel(void);
66 extern asmlinkage void handle_ades(void);
67 extern asmlinkage void handle_ibe(void);
68 extern asmlinkage void handle_dbe(void);
69 extern asmlinkage void handle_sys(void);
70 extern asmlinkage void handle_bp(void);
71 extern asmlinkage void handle_ri(void);
72 extern asmlinkage void handle_ri_rdhwr_vivt(void);
73 extern asmlinkage void handle_ri_rdhwr(void);
74 extern asmlinkage void handle_cpu(void);
75 extern asmlinkage void handle_ov(void);
76 extern asmlinkage void handle_tr(void);
77 extern asmlinkage void handle_fpe(void);
78 extern asmlinkage void handle_mdmx(void);
79 extern asmlinkage void handle_watch(void);
80 extern asmlinkage void handle_mt(void);
81 extern asmlinkage void handle_dsp(void);
82 extern asmlinkage void handle_mcheck(void);
83 extern asmlinkage void handle_reserved(void);
84
85 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
86 struct mips_fpu_struct *ctx, int has_fpu,
87 void *__user *fault_addr);
88
89 void (*board_be_init)(void);
90 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
91 void (*board_nmi_handler_setup)(void);
92 void (*board_ejtag_handler_setup)(void);
93 void (*board_bind_eic_interrupt)(int irq, int regset);
94 void (*board_ebase_setup)(void);
95
96
97 static void show_raw_backtrace(unsigned long reg29)
98 {
99 unsigned long *sp = (unsigned long *)(reg29 & ~3);
100 unsigned long addr;
101
102 printk("Call Trace:");
103 #ifdef CONFIG_KALLSYMS
104 printk("\n");
105 #endif
106 while (!kstack_end(sp)) {
107 unsigned long __user *p =
108 (unsigned long __user *)(unsigned long)sp++;
109 if (__get_user(addr, p)) {
110 printk(" (Bad stack address)");
111 break;
112 }
113 if (__kernel_text_address(addr))
114 print_ip_sym(addr);
115 }
116 printk("\n");
117 }
118
119 #ifdef CONFIG_KALLSYMS
120 int raw_show_trace;
121 static int __init set_raw_show_trace(char *str)
122 {
123 raw_show_trace = 1;
124 return 1;
125 }
126 __setup("raw_show_trace", set_raw_show_trace);
127 #endif
128
129 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
130 {
131 unsigned long sp = regs->regs[29];
132 unsigned long ra = regs->regs[31];
133 unsigned long pc = regs->cp0_epc;
134
135 if (raw_show_trace || !__kernel_text_address(pc)) {
136 show_raw_backtrace(sp);
137 return;
138 }
139 printk("Call Trace:\n");
140 do {
141 print_ip_sym(pc);
142 pc = unwind_stack(task, &sp, pc, &ra);
143 } while (pc);
144 printk("\n");
145 }
146
147 /*
148 * This routine abuses get_user()/put_user() to reference pointers
149 * with at least a bit of error checking ...
150 */
151 static void show_stacktrace(struct task_struct *task,
152 const struct pt_regs *regs)
153 {
154 const int field = 2 * sizeof(unsigned long);
155 long stackdata;
156 int i;
157 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
158
159 printk("Stack :");
160 i = 0;
161 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
162 if (i && ((i % (64 / field)) == 0))
163 printk("\n ");
164 if (i > 39) {
165 printk(" ...");
166 break;
167 }
168
169 if (__get_user(stackdata, sp++)) {
170 printk(" (Bad stack address)");
171 break;
172 }
173
174 printk(" %0*lx", field, stackdata);
175 i++;
176 }
177 printk("\n");
178 show_backtrace(task, regs);
179 }
180
181 void show_stack(struct task_struct *task, unsigned long *sp)
182 {
183 struct pt_regs regs;
184 if (sp) {
185 regs.regs[29] = (unsigned long)sp;
186 regs.regs[31] = 0;
187 regs.cp0_epc = 0;
188 } else {
189 if (task && task != current) {
190 regs.regs[29] = task->thread.reg29;
191 regs.regs[31] = 0;
192 regs.cp0_epc = task->thread.reg31;
193 #ifdef CONFIG_KGDB_KDB
194 } else if (atomic_read(&kgdb_active) != -1 &&
195 kdb_current_regs) {
196 memcpy(&regs, kdb_current_regs, sizeof(regs));
197 #endif /* CONFIG_KGDB_KDB */
198 } else {
199 prepare_frametrace(&regs);
200 }
201 }
202 show_stacktrace(task, &regs);
203 }
204
205 /*
206 * The architecture-independent dump_stack generator
207 */
208 void dump_stack(void)
209 {
210 struct pt_regs regs;
211
212 prepare_frametrace(&regs);
213 show_backtrace(current, &regs);
214 }
215
216 EXPORT_SYMBOL(dump_stack);
217
218 static void show_code(unsigned int __user *pc)
219 {
220 long i;
221 unsigned short __user *pc16 = NULL;
222
223 printk("\nCode:");
224
225 if ((unsigned long)pc & 1)
226 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
227 for(i = -3 ; i < 6 ; i++) {
228 unsigned int insn;
229 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
230 printk(" (Bad address in epc)\n");
231 break;
232 }
233 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
234 }
235 }
236
237 static void __show_regs(const struct pt_regs *regs)
238 {
239 const int field = 2 * sizeof(unsigned long);
240 unsigned int cause = regs->cp0_cause;
241 int i;
242
243 printk("Cpu %d\n", smp_processor_id());
244
245 /*
246 * Saved main processor registers
247 */
248 for (i = 0; i < 32; ) {
249 if ((i % 4) == 0)
250 printk("$%2d :", i);
251 if (i == 0)
252 printk(" %0*lx", field, 0UL);
253 else if (i == 26 || i == 27)
254 printk(" %*s", field, "");
255 else
256 printk(" %0*lx", field, regs->regs[i]);
257
258 i++;
259 if ((i % 4) == 0)
260 printk("\n");
261 }
262
263 #ifdef CONFIG_CPU_HAS_SMARTMIPS
264 printk("Acx : %0*lx\n", field, regs->acx);
265 #endif
266 printk("Hi : %0*lx\n", field, regs->hi);
267 printk("Lo : %0*lx\n", field, regs->lo);
268
269 /*
270 * Saved cp0 registers
271 */
272 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
273 (void *) regs->cp0_epc);
274 printk(" %s\n", print_tainted());
275 printk("ra : %0*lx %pS\n", field, regs->regs[31],
276 (void *) regs->regs[31]);
277
278 printk("Status: %08x ", (uint32_t) regs->cp0_status);
279
280 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
281 if (regs->cp0_status & ST0_KUO)
282 printk("KUo ");
283 if (regs->cp0_status & ST0_IEO)
284 printk("IEo ");
285 if (regs->cp0_status & ST0_KUP)
286 printk("KUp ");
287 if (regs->cp0_status & ST0_IEP)
288 printk("IEp ");
289 if (regs->cp0_status & ST0_KUC)
290 printk("KUc ");
291 if (regs->cp0_status & ST0_IEC)
292 printk("IEc ");
293 } else {
294 if (regs->cp0_status & ST0_KX)
295 printk("KX ");
296 if (regs->cp0_status & ST0_SX)
297 printk("SX ");
298 if (regs->cp0_status & ST0_UX)
299 printk("UX ");
300 switch (regs->cp0_status & ST0_KSU) {
301 case KSU_USER:
302 printk("USER ");
303 break;
304 case KSU_SUPERVISOR:
305 printk("SUPERVISOR ");
306 break;
307 case KSU_KERNEL:
308 printk("KERNEL ");
309 break;
310 default:
311 printk("BAD_MODE ");
312 break;
313 }
314 if (regs->cp0_status & ST0_ERL)
315 printk("ERL ");
316 if (regs->cp0_status & ST0_EXL)
317 printk("EXL ");
318 if (regs->cp0_status & ST0_IE)
319 printk("IE ");
320 }
321 printk("\n");
322
323 printk("Cause : %08x\n", cause);
324
325 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
326 if (1 <= cause && cause <= 5)
327 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
328
329 printk("PrId : %08x (%s)\n", read_c0_prid(),
330 cpu_name_string());
331 }
332
333 /*
334 * FIXME: really the generic show_regs should take a const pointer argument.
335 */
336 void show_regs(struct pt_regs *regs)
337 {
338 __show_regs((struct pt_regs *)regs);
339 }
340
341 void show_registers(struct pt_regs *regs)
342 {
343 const int field = 2 * sizeof(unsigned long);
344
345 __show_regs(regs);
346 print_modules();
347 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
348 current->comm, current->pid, current_thread_info(), current,
349 field, current_thread_info()->tp_value);
350 if (cpu_has_userlocal) {
351 unsigned long tls;
352
353 tls = read_c0_userlocal();
354 if (tls != current_thread_info()->tp_value)
355 printk("*HwTLS: %0*lx\n", field, tls);
356 }
357
358 show_stacktrace(current, regs);
359 show_code((unsigned int __user *) regs->cp0_epc);
360 printk("\n");
361 }
362
363 static int regs_to_trapnr(struct pt_regs *regs)
364 {
365 return (regs->cp0_cause >> 2) & 0x1f;
366 }
367
368 static DEFINE_RAW_SPINLOCK(die_lock);
369
370 void __noreturn die(const char *str, struct pt_regs *regs)
371 {
372 static int die_counter;
373 int sig = SIGSEGV;
374 #ifdef CONFIG_MIPS_MT_SMTC
375 unsigned long dvpret;
376 #endif /* CONFIG_MIPS_MT_SMTC */
377
378 oops_enter();
379
380 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
381 sig = 0;
382
383 console_verbose();
384 raw_spin_lock_irq(&die_lock);
385 #ifdef CONFIG_MIPS_MT_SMTC
386 dvpret = dvpe();
387 #endif /* CONFIG_MIPS_MT_SMTC */
388 bust_spinlocks(1);
389 #ifdef CONFIG_MIPS_MT_SMTC
390 mips_mt_regdump(dvpret);
391 #endif /* CONFIG_MIPS_MT_SMTC */
392
393 printk("%s[#%d]:\n", str, ++die_counter);
394 show_registers(regs);
395 add_taint(TAINT_DIE);
396 raw_spin_unlock_irq(&die_lock);
397
398 oops_exit();
399
400 if (in_interrupt())
401 panic("Fatal exception in interrupt");
402
403 if (panic_on_oops) {
404 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
405 ssleep(5);
406 panic("Fatal exception");
407 }
408
409 do_exit(sig);
410 }
411
412 extern struct exception_table_entry __start___dbe_table[];
413 extern struct exception_table_entry __stop___dbe_table[];
414
415 __asm__(
416 " .section __dbe_table, \"a\"\n"
417 " .previous \n");
418
419 /* Given an address, look for it in the exception tables. */
420 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
421 {
422 const struct exception_table_entry *e;
423
424 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
425 if (!e)
426 e = search_module_dbetables(addr);
427 return e;
428 }
429
430 asmlinkage void do_be(struct pt_regs *regs)
431 {
432 const int field = 2 * sizeof(unsigned long);
433 const struct exception_table_entry *fixup = NULL;
434 int data = regs->cp0_cause & 4;
435 int action = MIPS_BE_FATAL;
436
437 /* XXX For now. Fixme, this searches the wrong table ... */
438 if (data && !user_mode(regs))
439 fixup = search_dbe_tables(exception_epc(regs));
440
441 if (fixup)
442 action = MIPS_BE_FIXUP;
443
444 if (board_be_handler)
445 action = board_be_handler(regs, fixup != NULL);
446
447 switch (action) {
448 case MIPS_BE_DISCARD:
449 return;
450 case MIPS_BE_FIXUP:
451 if (fixup) {
452 regs->cp0_epc = fixup->nextinsn;
453 return;
454 }
455 break;
456 default:
457 break;
458 }
459
460 /*
461 * Assume it would be too dangerous to continue ...
462 */
463 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
464 data ? "Data" : "Instruction",
465 field, regs->cp0_epc, field, regs->regs[31]);
466 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
467 == NOTIFY_STOP)
468 return;
469
470 die_if_kernel("Oops", regs);
471 force_sig(SIGBUS, current);
472 }
473
474 /*
475 * ll/sc, rdhwr, sync emulation
476 */
477
478 #define OPCODE 0xfc000000
479 #define BASE 0x03e00000
480 #define RT 0x001f0000
481 #define OFFSET 0x0000ffff
482 #define LL 0xc0000000
483 #define SC 0xe0000000
484 #define SPEC0 0x00000000
485 #define SPEC3 0x7c000000
486 #define RD 0x0000f800
487 #define FUNC 0x0000003f
488 #define SYNC 0x0000000f
489 #define RDHWR 0x0000003b
490
491 /*
492 * The ll_bit is cleared by r*_switch.S
493 */
494
495 unsigned int ll_bit;
496 struct task_struct *ll_task;
497
498 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
499 {
500 unsigned long value, __user *vaddr;
501 long offset;
502
503 /*
504 * analyse the ll instruction that just caused a ri exception
505 * and put the referenced address to addr.
506 */
507
508 /* sign extend offset */
509 offset = opcode & OFFSET;
510 offset <<= 16;
511 offset >>= 16;
512
513 vaddr = (unsigned long __user *)
514 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
515
516 if ((unsigned long)vaddr & 3)
517 return SIGBUS;
518 if (get_user(value, vaddr))
519 return SIGSEGV;
520
521 preempt_disable();
522
523 if (ll_task == NULL || ll_task == current) {
524 ll_bit = 1;
525 } else {
526 ll_bit = 0;
527 }
528 ll_task = current;
529
530 preempt_enable();
531
532 regs->regs[(opcode & RT) >> 16] = value;
533
534 return 0;
535 }
536
537 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
538 {
539 unsigned long __user *vaddr;
540 unsigned long reg;
541 long offset;
542
543 /*
544 * analyse the sc instruction that just caused a ri exception
545 * and put the referenced address to addr.
546 */
547
548 /* sign extend offset */
549 offset = opcode & OFFSET;
550 offset <<= 16;
551 offset >>= 16;
552
553 vaddr = (unsigned long __user *)
554 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
555 reg = (opcode & RT) >> 16;
556
557 if ((unsigned long)vaddr & 3)
558 return SIGBUS;
559
560 preempt_disable();
561
562 if (ll_bit == 0 || ll_task != current) {
563 regs->regs[reg] = 0;
564 preempt_enable();
565 return 0;
566 }
567
568 preempt_enable();
569
570 if (put_user(regs->regs[reg], vaddr))
571 return SIGSEGV;
572
573 regs->regs[reg] = 1;
574
575 return 0;
576 }
577
578 /*
579 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
580 * opcodes are supposed to result in coprocessor unusable exceptions if
581 * executed on ll/sc-less processors. That's the theory. In practice a
582 * few processors such as NEC's VR4100 throw reserved instruction exceptions
583 * instead, so we're doing the emulation thing in both exception handlers.
584 */
585 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
586 {
587 if ((opcode & OPCODE) == LL) {
588 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
589 1, regs, 0);
590 return simulate_ll(regs, opcode);
591 }
592 if ((opcode & OPCODE) == SC) {
593 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
594 1, regs, 0);
595 return simulate_sc(regs, opcode);
596 }
597
598 return -1; /* Must be something else ... */
599 }
600
601 /*
602 * Simulate trapping 'rdhwr' instructions to provide user accessible
603 * registers not implemented in hardware.
604 */
605 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
606 {
607 struct thread_info *ti = task_thread_info(current);
608
609 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
610 int rd = (opcode & RD) >> 11;
611 int rt = (opcode & RT) >> 16;
612 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
613 1, regs, 0);
614 switch (rd) {
615 case 0: /* CPU number */
616 regs->regs[rt] = smp_processor_id();
617 return 0;
618 case 1: /* SYNCI length */
619 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
620 current_cpu_data.icache.linesz);
621 return 0;
622 case 2: /* Read count register */
623 regs->regs[rt] = read_c0_count();
624 return 0;
625 case 3: /* Count register resolution */
626 switch (current_cpu_data.cputype) {
627 case CPU_20KC:
628 case CPU_25KF:
629 regs->regs[rt] = 1;
630 break;
631 default:
632 regs->regs[rt] = 2;
633 }
634 return 0;
635 case 29:
636 regs->regs[rt] = ti->tp_value;
637 return 0;
638 default:
639 return -1;
640 }
641 }
642
643 /* Not ours. */
644 return -1;
645 }
646
647 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
648 {
649 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
650 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
651 1, regs, 0);
652 return 0;
653 }
654
655 return -1; /* Must be something else ... */
656 }
657
658 asmlinkage void do_ov(struct pt_regs *regs)
659 {
660 siginfo_t info;
661
662 die_if_kernel("Integer overflow", regs);
663
664 info.si_code = FPE_INTOVF;
665 info.si_signo = SIGFPE;
666 info.si_errno = 0;
667 info.si_addr = (void __user *) regs->cp0_epc;
668 force_sig_info(SIGFPE, &info, current);
669 }
670
671 static int process_fpemu_return(int sig, void __user *fault_addr)
672 {
673 if (sig == SIGSEGV || sig == SIGBUS) {
674 struct siginfo si = {0};
675 si.si_addr = fault_addr;
676 si.si_signo = sig;
677 if (sig == SIGSEGV) {
678 if (find_vma(current->mm, (unsigned long)fault_addr))
679 si.si_code = SEGV_ACCERR;
680 else
681 si.si_code = SEGV_MAPERR;
682 } else {
683 si.si_code = BUS_ADRERR;
684 }
685 force_sig_info(sig, &si, current);
686 return 1;
687 } else if (sig) {
688 force_sig(sig, current);
689 return 1;
690 } else {
691 return 0;
692 }
693 }
694
695 /*
696 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
697 */
698 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
699 {
700 siginfo_t info = {0};
701
702 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
703 == NOTIFY_STOP)
704 return;
705 die_if_kernel("FP exception in kernel code", regs);
706
707 if (fcr31 & FPU_CSR_UNI_X) {
708 int sig;
709 void __user *fault_addr = NULL;
710
711 /*
712 * Unimplemented operation exception. If we've got the full
713 * software emulator on-board, let's use it...
714 *
715 * Force FPU to dump state into task/thread context. We're
716 * moving a lot of data here for what is probably a single
717 * instruction, but the alternative is to pre-decode the FP
718 * register operands before invoking the emulator, which seems
719 * a bit extreme for what should be an infrequent event.
720 */
721 /* Ensure 'resume' not overwrite saved fp context again. */
722 lose_fpu(1);
723
724 /* Run the emulator */
725 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
726 &fault_addr);
727
728 /*
729 * We can't allow the emulated instruction to leave any of
730 * the cause bit set in $fcr31.
731 */
732 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
733
734 /* Restore the hardware register state */
735 own_fpu(1); /* Using the FPU again. */
736
737 /* If something went wrong, signal */
738 process_fpemu_return(sig, fault_addr);
739
740 return;
741 } else if (fcr31 & FPU_CSR_INV_X)
742 info.si_code = FPE_FLTINV;
743 else if (fcr31 & FPU_CSR_DIV_X)
744 info.si_code = FPE_FLTDIV;
745 else if (fcr31 & FPU_CSR_OVF_X)
746 info.si_code = FPE_FLTOVF;
747 else if (fcr31 & FPU_CSR_UDF_X)
748 info.si_code = FPE_FLTUND;
749 else if (fcr31 & FPU_CSR_INE_X)
750 info.si_code = FPE_FLTRES;
751 else
752 info.si_code = __SI_FAULT;
753 info.si_signo = SIGFPE;
754 info.si_errno = 0;
755 info.si_addr = (void __user *) regs->cp0_epc;
756 force_sig_info(SIGFPE, &info, current);
757 }
758
759 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
760 const char *str)
761 {
762 siginfo_t info;
763 char b[40];
764
765 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
766 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
767 return;
768 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
769
770 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
771 return;
772
773 /*
774 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
775 * insns, even for trap and break codes that indicate arithmetic
776 * failures. Weird ...
777 * But should we continue the brokenness??? --macro
778 */
779 switch (code) {
780 case BRK_OVERFLOW:
781 case BRK_DIVZERO:
782 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
783 die_if_kernel(b, regs);
784 if (code == BRK_DIVZERO)
785 info.si_code = FPE_INTDIV;
786 else
787 info.si_code = FPE_INTOVF;
788 info.si_signo = SIGFPE;
789 info.si_errno = 0;
790 info.si_addr = (void __user *) regs->cp0_epc;
791 force_sig_info(SIGFPE, &info, current);
792 break;
793 case BRK_BUG:
794 die_if_kernel("Kernel bug detected", regs);
795 force_sig(SIGTRAP, current);
796 break;
797 case BRK_MEMU:
798 /*
799 * Address errors may be deliberately induced by the FPU
800 * emulator to retake control of the CPU after executing the
801 * instruction in the delay slot of an emulated branch.
802 *
803 * Terminate if exception was recognized as a delay slot return
804 * otherwise handle as normal.
805 */
806 if (do_dsemulret(regs))
807 return;
808
809 die_if_kernel("Math emu break/trap", regs);
810 force_sig(SIGTRAP, current);
811 break;
812 default:
813 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
814 die_if_kernel(b, regs);
815 force_sig(SIGTRAP, current);
816 }
817 }
818
819 asmlinkage void do_bp(struct pt_regs *regs)
820 {
821 unsigned int opcode, bcode;
822
823 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
824 goto out_sigsegv;
825
826 /*
827 * There is the ancient bug in the MIPS assemblers that the break
828 * code starts left to bit 16 instead to bit 6 in the opcode.
829 * Gas is bug-compatible, but not always, grrr...
830 * We handle both cases with a simple heuristics. --macro
831 */
832 bcode = ((opcode >> 6) & ((1 << 20) - 1));
833 if (bcode >= (1 << 10))
834 bcode >>= 10;
835
836 /*
837 * notify the kprobe handlers, if instruction is likely to
838 * pertain to them.
839 */
840 switch (bcode) {
841 case BRK_KPROBE_BP:
842 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
843 return;
844 else
845 break;
846 case BRK_KPROBE_SSTEPBP:
847 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
848 return;
849 else
850 break;
851 default:
852 break;
853 }
854
855 do_trap_or_bp(regs, bcode, "Break");
856 return;
857
858 out_sigsegv:
859 force_sig(SIGSEGV, current);
860 }
861
862 asmlinkage void do_tr(struct pt_regs *regs)
863 {
864 unsigned int opcode, tcode = 0;
865
866 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
867 goto out_sigsegv;
868
869 /* Immediate versions don't provide a code. */
870 if (!(opcode & OPCODE))
871 tcode = ((opcode >> 6) & ((1 << 10) - 1));
872
873 do_trap_or_bp(regs, tcode, "Trap");
874 return;
875
876 out_sigsegv:
877 force_sig(SIGSEGV, current);
878 }
879
880 asmlinkage void do_ri(struct pt_regs *regs)
881 {
882 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
883 unsigned long old_epc = regs->cp0_epc;
884 unsigned int opcode = 0;
885 int status = -1;
886
887 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
888 == NOTIFY_STOP)
889 return;
890
891 die_if_kernel("Reserved instruction in kernel code", regs);
892
893 if (unlikely(compute_return_epc(regs) < 0))
894 return;
895
896 if (unlikely(get_user(opcode, epc) < 0))
897 status = SIGSEGV;
898
899 if (!cpu_has_llsc && status < 0)
900 status = simulate_llsc(regs, opcode);
901
902 if (status < 0)
903 status = simulate_rdhwr(regs, opcode);
904
905 if (status < 0)
906 status = simulate_sync(regs, opcode);
907
908 if (status < 0)
909 status = SIGILL;
910
911 if (unlikely(status > 0)) {
912 regs->cp0_epc = old_epc; /* Undo skip-over. */
913 force_sig(status, current);
914 }
915 }
916
917 /*
918 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
919 * emulated more than some threshold number of instructions, force migration to
920 * a "CPU" that has FP support.
921 */
922 static void mt_ase_fp_affinity(void)
923 {
924 #ifdef CONFIG_MIPS_MT_FPAFF
925 if (mt_fpemul_threshold > 0 &&
926 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
927 /*
928 * If there's no FPU present, or if the application has already
929 * restricted the allowed set to exclude any CPUs with FPUs,
930 * we'll skip the procedure.
931 */
932 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
933 cpumask_t tmask;
934
935 current->thread.user_cpus_allowed
936 = current->cpus_allowed;
937 cpus_and(tmask, current->cpus_allowed,
938 mt_fpu_cpumask);
939 set_cpus_allowed_ptr(current, &tmask);
940 set_thread_flag(TIF_FPUBOUND);
941 }
942 }
943 #endif /* CONFIG_MIPS_MT_FPAFF */
944 }
945
946 /*
947 * No lock; only written during early bootup by CPU 0.
948 */
949 static RAW_NOTIFIER_HEAD(cu2_chain);
950
951 int __ref register_cu2_notifier(struct notifier_block *nb)
952 {
953 return raw_notifier_chain_register(&cu2_chain, nb);
954 }
955
956 int cu2_notifier_call_chain(unsigned long val, void *v)
957 {
958 return raw_notifier_call_chain(&cu2_chain, val, v);
959 }
960
961 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
962 void *data)
963 {
964 struct pt_regs *regs = data;
965
966 switch (action) {
967 default:
968 die_if_kernel("Unhandled kernel unaligned access or invalid "
969 "instruction", regs);
970 /* Fall through */
971
972 case CU2_EXCEPTION:
973 force_sig(SIGILL, current);
974 }
975
976 return NOTIFY_OK;
977 }
978
979 asmlinkage void do_cpu(struct pt_regs *regs)
980 {
981 unsigned int __user *epc;
982 unsigned long old_epc;
983 unsigned int opcode;
984 unsigned int cpid;
985 int status;
986 unsigned long __maybe_unused flags;
987
988 die_if_kernel("do_cpu invoked from kernel context!", regs);
989
990 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
991
992 switch (cpid) {
993 case 0:
994 epc = (unsigned int __user *)exception_epc(regs);
995 old_epc = regs->cp0_epc;
996 opcode = 0;
997 status = -1;
998
999 if (unlikely(compute_return_epc(regs) < 0))
1000 return;
1001
1002 if (unlikely(get_user(opcode, epc) < 0))
1003 status = SIGSEGV;
1004
1005 if (!cpu_has_llsc && status < 0)
1006 status = simulate_llsc(regs, opcode);
1007
1008 if (status < 0)
1009 status = simulate_rdhwr(regs, opcode);
1010
1011 if (status < 0)
1012 status = SIGILL;
1013
1014 if (unlikely(status > 0)) {
1015 regs->cp0_epc = old_epc; /* Undo skip-over. */
1016 force_sig(status, current);
1017 }
1018
1019 return;
1020
1021 case 1:
1022 if (used_math()) /* Using the FPU again. */
1023 own_fpu(1);
1024 else { /* First time FPU user. */
1025 init_fpu();
1026 set_used_math();
1027 }
1028
1029 if (!raw_cpu_has_fpu) {
1030 int sig;
1031 void __user *fault_addr = NULL;
1032 sig = fpu_emulator_cop1Handler(regs,
1033 &current->thread.fpu,
1034 0, &fault_addr);
1035 if (!process_fpemu_return(sig, fault_addr))
1036 mt_ase_fp_affinity();
1037 }
1038
1039 return;
1040
1041 case 2:
1042 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1043 return;
1044
1045 case 3:
1046 break;
1047 }
1048
1049 force_sig(SIGILL, current);
1050 }
1051
1052 asmlinkage void do_mdmx(struct pt_regs *regs)
1053 {
1054 force_sig(SIGILL, current);
1055 }
1056
1057 /*
1058 * Called with interrupts disabled.
1059 */
1060 asmlinkage void do_watch(struct pt_regs *regs)
1061 {
1062 u32 cause;
1063
1064 /*
1065 * Clear WP (bit 22) bit of cause register so we don't loop
1066 * forever.
1067 */
1068 cause = read_c0_cause();
1069 cause &= ~(1 << 22);
1070 write_c0_cause(cause);
1071
1072 /*
1073 * If the current thread has the watch registers loaded, save
1074 * their values and send SIGTRAP. Otherwise another thread
1075 * left the registers set, clear them and continue.
1076 */
1077 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1078 mips_read_watch_registers();
1079 local_irq_enable();
1080 force_sig(SIGTRAP, current);
1081 } else {
1082 mips_clear_watch_registers();
1083 local_irq_enable();
1084 }
1085 }
1086
1087 asmlinkage void do_mcheck(struct pt_regs *regs)
1088 {
1089 const int field = 2 * sizeof(unsigned long);
1090 int multi_match = regs->cp0_status & ST0_TS;
1091
1092 show_regs(regs);
1093
1094 if (multi_match) {
1095 printk("Index : %0x\n", read_c0_index());
1096 printk("Pagemask: %0x\n", read_c0_pagemask());
1097 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1098 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1099 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1100 printk("\n");
1101 dump_tlb_all();
1102 }
1103
1104 show_code((unsigned int __user *) regs->cp0_epc);
1105
1106 /*
1107 * Some chips may have other causes of machine check (e.g. SB1
1108 * graduation timer)
1109 */
1110 panic("Caught Machine Check exception - %scaused by multiple "
1111 "matching entries in the TLB.",
1112 (multi_match) ? "" : "not ");
1113 }
1114
1115 asmlinkage void do_mt(struct pt_regs *regs)
1116 {
1117 int subcode;
1118
1119 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1120 >> VPECONTROL_EXCPT_SHIFT;
1121 switch (subcode) {
1122 case 0:
1123 printk(KERN_DEBUG "Thread Underflow\n");
1124 break;
1125 case 1:
1126 printk(KERN_DEBUG "Thread Overflow\n");
1127 break;
1128 case 2:
1129 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1130 break;
1131 case 3:
1132 printk(KERN_DEBUG "Gating Storage Exception\n");
1133 break;
1134 case 4:
1135 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1136 break;
1137 case 5:
1138 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1139 break;
1140 default:
1141 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1142 subcode);
1143 break;
1144 }
1145 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1146
1147 force_sig(SIGILL, current);
1148 }
1149
1150
1151 asmlinkage void do_dsp(struct pt_regs *regs)
1152 {
1153 if (cpu_has_dsp)
1154 panic("Unexpected DSP exception");
1155
1156 force_sig(SIGILL, current);
1157 }
1158
1159 asmlinkage void do_reserved(struct pt_regs *regs)
1160 {
1161 /*
1162 * Game over - no way to handle this if it ever occurs. Most probably
1163 * caused by a new unknown cpu type or after another deadly
1164 * hard/software error.
1165 */
1166 show_regs(regs);
1167 panic("Caught reserved exception %ld - should not happen.",
1168 (regs->cp0_cause & 0x7f) >> 2);
1169 }
1170
1171 static int __initdata l1parity = 1;
1172 static int __init nol1parity(char *s)
1173 {
1174 l1parity = 0;
1175 return 1;
1176 }
1177 __setup("nol1par", nol1parity);
1178 static int __initdata l2parity = 1;
1179 static int __init nol2parity(char *s)
1180 {
1181 l2parity = 0;
1182 return 1;
1183 }
1184 __setup("nol2par", nol2parity);
1185
1186 /*
1187 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1188 * it different ways.
1189 */
1190 static inline void parity_protection_init(void)
1191 {
1192 switch (current_cpu_type()) {
1193 case CPU_24K:
1194 case CPU_34K:
1195 case CPU_74K:
1196 case CPU_1004K:
1197 {
1198 #define ERRCTL_PE 0x80000000
1199 #define ERRCTL_L2P 0x00800000
1200 unsigned long errctl;
1201 unsigned int l1parity_present, l2parity_present;
1202
1203 errctl = read_c0_ecc();
1204 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1205
1206 /* probe L1 parity support */
1207 write_c0_ecc(errctl | ERRCTL_PE);
1208 back_to_back_c0_hazard();
1209 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1210
1211 /* probe L2 parity support */
1212 write_c0_ecc(errctl|ERRCTL_L2P);
1213 back_to_back_c0_hazard();
1214 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1215
1216 if (l1parity_present && l2parity_present) {
1217 if (l1parity)
1218 errctl |= ERRCTL_PE;
1219 if (l1parity ^ l2parity)
1220 errctl |= ERRCTL_L2P;
1221 } else if (l1parity_present) {
1222 if (l1parity)
1223 errctl |= ERRCTL_PE;
1224 } else if (l2parity_present) {
1225 if (l2parity)
1226 errctl |= ERRCTL_L2P;
1227 } else {
1228 /* No parity available */
1229 }
1230
1231 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1232
1233 write_c0_ecc(errctl);
1234 back_to_back_c0_hazard();
1235 errctl = read_c0_ecc();
1236 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1237
1238 if (l1parity_present)
1239 printk(KERN_INFO "Cache parity protection %sabled\n",
1240 (errctl & ERRCTL_PE) ? "en" : "dis");
1241
1242 if (l2parity_present) {
1243 if (l1parity_present && l1parity)
1244 errctl ^= ERRCTL_L2P;
1245 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1246 (errctl & ERRCTL_L2P) ? "en" : "dis");
1247 }
1248 }
1249 break;
1250
1251 case CPU_5KC:
1252 write_c0_ecc(0x80000000);
1253 back_to_back_c0_hazard();
1254 /* Set the PE bit (bit 31) in the c0_errctl register. */
1255 printk(KERN_INFO "Cache parity protection %sabled\n",
1256 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1257 break;
1258 case CPU_20KC:
1259 case CPU_25KF:
1260 /* Clear the DE bit (bit 16) in the c0_status register. */
1261 printk(KERN_INFO "Enable cache parity protection for "
1262 "MIPS 20KC/25KF CPUs.\n");
1263 clear_c0_status(ST0_DE);
1264 break;
1265 default:
1266 break;
1267 }
1268 }
1269
1270 asmlinkage void cache_parity_error(void)
1271 {
1272 const int field = 2 * sizeof(unsigned long);
1273 unsigned int reg_val;
1274
1275 /* For the moment, report the problem and hang. */
1276 printk("Cache error exception:\n");
1277 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1278 reg_val = read_c0_cacheerr();
1279 printk("c0_cacheerr == %08x\n", reg_val);
1280
1281 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1282 reg_val & (1<<30) ? "secondary" : "primary",
1283 reg_val & (1<<31) ? "data" : "insn");
1284 printk("Error bits: %s%s%s%s%s%s%s\n",
1285 reg_val & (1<<29) ? "ED " : "",
1286 reg_val & (1<<28) ? "ET " : "",
1287 reg_val & (1<<26) ? "EE " : "",
1288 reg_val & (1<<25) ? "EB " : "",
1289 reg_val & (1<<24) ? "EI " : "",
1290 reg_val & (1<<23) ? "E1 " : "",
1291 reg_val & (1<<22) ? "E0 " : "");
1292 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1293
1294 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1295 if (reg_val & (1<<22))
1296 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1297
1298 if (reg_val & (1<<23))
1299 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1300 #endif
1301
1302 panic("Can't handle the cache error!");
1303 }
1304
1305 /*
1306 * SDBBP EJTAG debug exception handler.
1307 * We skip the instruction and return to the next instruction.
1308 */
1309 void ejtag_exception_handler(struct pt_regs *regs)
1310 {
1311 const int field = 2 * sizeof(unsigned long);
1312 unsigned long depc, old_epc;
1313 unsigned int debug;
1314
1315 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1316 depc = read_c0_depc();
1317 debug = read_c0_debug();
1318 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1319 if (debug & 0x80000000) {
1320 /*
1321 * In branch delay slot.
1322 * We cheat a little bit here and use EPC to calculate the
1323 * debug return address (DEPC). EPC is restored after the
1324 * calculation.
1325 */
1326 old_epc = regs->cp0_epc;
1327 regs->cp0_epc = depc;
1328 __compute_return_epc(regs);
1329 depc = regs->cp0_epc;
1330 regs->cp0_epc = old_epc;
1331 } else
1332 depc += 4;
1333 write_c0_depc(depc);
1334
1335 #if 0
1336 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1337 write_c0_debug(debug | 0x100);
1338 #endif
1339 }
1340
1341 /*
1342 * NMI exception handler.
1343 * No lock; only written during early bootup by CPU 0.
1344 */
1345 static RAW_NOTIFIER_HEAD(nmi_chain);
1346
1347 int register_nmi_notifier(struct notifier_block *nb)
1348 {
1349 return raw_notifier_chain_register(&nmi_chain, nb);
1350 }
1351
1352 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1353 {
1354 raw_notifier_call_chain(&nmi_chain, 0, regs);
1355 bust_spinlocks(1);
1356 printk("NMI taken!!!!\n");
1357 die("NMI", regs);
1358 }
1359
1360 #define VECTORSPACING 0x100 /* for EI/VI mode */
1361
1362 unsigned long ebase;
1363 unsigned long exception_handlers[32];
1364 unsigned long vi_handlers[64];
1365
1366 void __init *set_except_vector(int n, void *addr)
1367 {
1368 unsigned long handler = (unsigned long) addr;
1369 unsigned long old_handler = exception_handlers[n];
1370
1371 exception_handlers[n] = handler;
1372 if (n == 0 && cpu_has_divec) {
1373 unsigned long jump_mask = ~((1 << 28) - 1);
1374 u32 *buf = (u32 *)(ebase + 0x200);
1375 unsigned int k0 = 26;
1376 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1377 uasm_i_j(&buf, handler & ~jump_mask);
1378 uasm_i_nop(&buf);
1379 } else {
1380 UASM_i_LA(&buf, k0, handler);
1381 uasm_i_jr(&buf, k0);
1382 uasm_i_nop(&buf);
1383 }
1384 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1385 }
1386 return (void *)old_handler;
1387 }
1388
1389 static asmlinkage void do_default_vi(void)
1390 {
1391 show_regs(get_irq_regs());
1392 panic("Caught unexpected vectored interrupt.");
1393 }
1394
1395 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1396 {
1397 unsigned long handler;
1398 unsigned long old_handler = vi_handlers[n];
1399 int srssets = current_cpu_data.srsets;
1400 u32 *w;
1401 unsigned char *b;
1402
1403 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1404
1405 if (addr == NULL) {
1406 handler = (unsigned long) do_default_vi;
1407 srs = 0;
1408 } else
1409 handler = (unsigned long) addr;
1410 vi_handlers[n] = (unsigned long) addr;
1411
1412 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1413
1414 if (srs >= srssets)
1415 panic("Shadow register set %d not supported", srs);
1416
1417 if (cpu_has_veic) {
1418 if (board_bind_eic_interrupt)
1419 board_bind_eic_interrupt(n, srs);
1420 } else if (cpu_has_vint) {
1421 /* SRSMap is only defined if shadow sets are implemented */
1422 if (srssets > 1)
1423 change_c0_srsmap(0xf << n*4, srs << n*4);
1424 }
1425
1426 if (srs == 0) {
1427 /*
1428 * If no shadow set is selected then use the default handler
1429 * that does normal register saving and a standard interrupt exit
1430 */
1431
1432 extern char except_vec_vi, except_vec_vi_lui;
1433 extern char except_vec_vi_ori, except_vec_vi_end;
1434 extern char rollback_except_vec_vi;
1435 char *vec_start = (cpu_wait == r4k_wait) ?
1436 &rollback_except_vec_vi : &except_vec_vi;
1437 #ifdef CONFIG_MIPS_MT_SMTC
1438 /*
1439 * We need to provide the SMTC vectored interrupt handler
1440 * not only with the address of the handler, but with the
1441 * Status.IM bit to be masked before going there.
1442 */
1443 extern char except_vec_vi_mori;
1444 const int mori_offset = &except_vec_vi_mori - vec_start;
1445 #endif /* CONFIG_MIPS_MT_SMTC */
1446 const int handler_len = &except_vec_vi_end - vec_start;
1447 const int lui_offset = &except_vec_vi_lui - vec_start;
1448 const int ori_offset = &except_vec_vi_ori - vec_start;
1449
1450 if (handler_len > VECTORSPACING) {
1451 /*
1452 * Sigh... panicing won't help as the console
1453 * is probably not configured :(
1454 */
1455 panic("VECTORSPACING too small");
1456 }
1457
1458 memcpy(b, vec_start, handler_len);
1459 #ifdef CONFIG_MIPS_MT_SMTC
1460 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1461
1462 w = (u32 *)(b + mori_offset);
1463 *w = (*w & 0xffff0000) | (0x100 << n);
1464 #endif /* CONFIG_MIPS_MT_SMTC */
1465 w = (u32 *)(b + lui_offset);
1466 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1467 w = (u32 *)(b + ori_offset);
1468 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1469 local_flush_icache_range((unsigned long)b,
1470 (unsigned long)(b+handler_len));
1471 }
1472 else {
1473 /*
1474 * In other cases jump directly to the interrupt handler
1475 *
1476 * It is the handlers responsibility to save registers if required
1477 * (eg hi/lo) and return from the exception using "eret"
1478 */
1479 w = (u32 *)b;
1480 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1481 *w = 0;
1482 local_flush_icache_range((unsigned long)b,
1483 (unsigned long)(b+8));
1484 }
1485
1486 return (void *)old_handler;
1487 }
1488
1489 void *set_vi_handler(int n, vi_handler_t addr)
1490 {
1491 return set_vi_srs_handler(n, addr, 0);
1492 }
1493
1494 extern void cpu_cache_init(void);
1495 extern void tlb_init(void);
1496 extern void flush_tlb_handlers(void);
1497
1498 /*
1499 * Timer interrupt
1500 */
1501 int cp0_compare_irq;
1502 int cp0_compare_irq_shift;
1503
1504 /*
1505 * Performance counter IRQ or -1 if shared with timer
1506 */
1507 int cp0_perfcount_irq;
1508 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1509
1510 static int __cpuinitdata noulri;
1511
1512 static int __init ulri_disable(char *s)
1513 {
1514 pr_info("Disabling ulri\n");
1515 noulri = 1;
1516
1517 return 1;
1518 }
1519 __setup("noulri", ulri_disable);
1520
1521 void __cpuinit per_cpu_trap_init(void)
1522 {
1523 unsigned int cpu = smp_processor_id();
1524 unsigned int status_set = ST0_CU0;
1525 unsigned int hwrena = cpu_hwrena_impl_bits;
1526 #ifdef CONFIG_MIPS_MT_SMTC
1527 int secondaryTC = 0;
1528 int bootTC = (cpu == 0);
1529
1530 /*
1531 * Only do per_cpu_trap_init() for first TC of Each VPE.
1532 * Note that this hack assumes that the SMTC init code
1533 * assigns TCs consecutively and in ascending order.
1534 */
1535
1536 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1537 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1538 secondaryTC = 1;
1539 #endif /* CONFIG_MIPS_MT_SMTC */
1540
1541 /*
1542 * Disable coprocessors and select 32-bit or 64-bit addressing
1543 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1544 * flag that some firmware may have left set and the TS bit (for
1545 * IP27). Set XX for ISA IV code to work.
1546 */
1547 #ifdef CONFIG_64BIT
1548 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1549 #endif
1550 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1551 status_set |= ST0_XX;
1552 if (cpu_has_dsp)
1553 status_set |= ST0_MX;
1554
1555 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1556 status_set);
1557
1558 if (cpu_has_mips_r2)
1559 hwrena |= 0x0000000f;
1560
1561 if (!noulri && cpu_has_userlocal)
1562 hwrena |= (1 << 29);
1563
1564 if (hwrena)
1565 write_c0_hwrena(hwrena);
1566
1567 #ifdef CONFIG_MIPS_MT_SMTC
1568 if (!secondaryTC) {
1569 #endif /* CONFIG_MIPS_MT_SMTC */
1570
1571 if (cpu_has_veic || cpu_has_vint) {
1572 unsigned long sr = set_c0_status(ST0_BEV);
1573 write_c0_ebase(ebase);
1574 write_c0_status(sr);
1575 /* Setting vector spacing enables EI/VI mode */
1576 change_c0_intctl(0x3e0, VECTORSPACING);
1577 }
1578 if (cpu_has_divec) {
1579 if (cpu_has_mipsmt) {
1580 unsigned int vpflags = dvpe();
1581 set_c0_cause(CAUSEF_IV);
1582 evpe(vpflags);
1583 } else
1584 set_c0_cause(CAUSEF_IV);
1585 }
1586
1587 /*
1588 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1589 *
1590 * o read IntCtl.IPTI to determine the timer interrupt
1591 * o read IntCtl.IPPCI to determine the performance counter interrupt
1592 */
1593 if (cpu_has_mips_r2) {
1594 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1595 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1596 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1597 if (cp0_perfcount_irq == cp0_compare_irq)
1598 cp0_perfcount_irq = -1;
1599 } else {
1600 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1601 cp0_compare_irq_shift = cp0_compare_irq;
1602 cp0_perfcount_irq = -1;
1603 }
1604
1605 #ifdef CONFIG_MIPS_MT_SMTC
1606 }
1607 #endif /* CONFIG_MIPS_MT_SMTC */
1608
1609 if (!cpu_data[cpu].asid_cache)
1610 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1611
1612 atomic_inc(&init_mm.mm_count);
1613 current->active_mm = &init_mm;
1614 BUG_ON(current->mm);
1615 enter_lazy_tlb(&init_mm, current);
1616
1617 #ifdef CONFIG_MIPS_MT_SMTC
1618 if (bootTC) {
1619 #endif /* CONFIG_MIPS_MT_SMTC */
1620 cpu_cache_init();
1621 tlb_init();
1622 #ifdef CONFIG_MIPS_MT_SMTC
1623 } else if (!secondaryTC) {
1624 /*
1625 * First TC in non-boot VPE must do subset of tlb_init()
1626 * for MMU countrol registers.
1627 */
1628 write_c0_pagemask(PM_DEFAULT_MASK);
1629 write_c0_wired(0);
1630 }
1631 #endif /* CONFIG_MIPS_MT_SMTC */
1632 TLBMISS_HANDLER_SETUP();
1633 }
1634
1635 /* Install CPU exception handler */
1636 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1637 {
1638 memcpy((void *)(ebase + offset), addr, size);
1639 local_flush_icache_range(ebase + offset, ebase + offset + size);
1640 }
1641
1642 static char panic_null_cerr[] __cpuinitdata =
1643 "Trying to set NULL cache error exception handler";
1644
1645 /*
1646 * Install uncached CPU exception handler.
1647 * This is suitable only for the cache error exception which is the only
1648 * exception handler that is being run uncached.
1649 */
1650 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1651 unsigned long size)
1652 {
1653 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1654
1655 if (!addr)
1656 panic(panic_null_cerr);
1657
1658 memcpy((void *)(uncached_ebase + offset), addr, size);
1659 }
1660
1661 static int __initdata rdhwr_noopt;
1662 static int __init set_rdhwr_noopt(char *str)
1663 {
1664 rdhwr_noopt = 1;
1665 return 1;
1666 }
1667
1668 __setup("rdhwr_noopt", set_rdhwr_noopt);
1669
1670 void __init trap_init(void)
1671 {
1672 extern char except_vec3_generic, except_vec3_r4000;
1673 extern char except_vec4;
1674 unsigned long i;
1675 int rollback;
1676
1677 check_wait();
1678 rollback = (cpu_wait == r4k_wait);
1679
1680 #if defined(CONFIG_KGDB)
1681 if (kgdb_early_setup)
1682 return; /* Already done */
1683 #endif
1684
1685 if (cpu_has_veic || cpu_has_vint) {
1686 unsigned long size = 0x200 + VECTORSPACING*64;
1687 ebase = (unsigned long)
1688 __alloc_bootmem(size, 1 << fls(size), 0);
1689 } else {
1690 ebase = CKSEG0;
1691 if (cpu_has_mips_r2)
1692 ebase += (read_c0_ebase() & 0x3ffff000);
1693 }
1694
1695 if (board_ebase_setup)
1696 board_ebase_setup();
1697 per_cpu_trap_init();
1698
1699 /*
1700 * Copy the generic exception handlers to their final destination.
1701 * This will be overriden later as suitable for a particular
1702 * configuration.
1703 */
1704 set_handler(0x180, &except_vec3_generic, 0x80);
1705
1706 /*
1707 * Setup default vectors
1708 */
1709 for (i = 0; i <= 31; i++)
1710 set_except_vector(i, handle_reserved);
1711
1712 /*
1713 * Copy the EJTAG debug exception vector handler code to it's final
1714 * destination.
1715 */
1716 if (cpu_has_ejtag && board_ejtag_handler_setup)
1717 board_ejtag_handler_setup();
1718
1719 /*
1720 * Only some CPUs have the watch exceptions.
1721 */
1722 if (cpu_has_watch)
1723 set_except_vector(23, handle_watch);
1724
1725 /*
1726 * Initialise interrupt handlers
1727 */
1728 if (cpu_has_veic || cpu_has_vint) {
1729 int nvec = cpu_has_veic ? 64 : 8;
1730 for (i = 0; i < nvec; i++)
1731 set_vi_handler(i, NULL);
1732 }
1733 else if (cpu_has_divec)
1734 set_handler(0x200, &except_vec4, 0x8);
1735
1736 /*
1737 * Some CPUs can enable/disable for cache parity detection, but does
1738 * it different ways.
1739 */
1740 parity_protection_init();
1741
1742 /*
1743 * The Data Bus Errors / Instruction Bus Errors are signaled
1744 * by external hardware. Therefore these two exceptions
1745 * may have board specific handlers.
1746 */
1747 if (board_be_init)
1748 board_be_init();
1749
1750 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1751 set_except_vector(1, handle_tlbm);
1752 set_except_vector(2, handle_tlbl);
1753 set_except_vector(3, handle_tlbs);
1754
1755 set_except_vector(4, handle_adel);
1756 set_except_vector(5, handle_ades);
1757
1758 set_except_vector(6, handle_ibe);
1759 set_except_vector(7, handle_dbe);
1760
1761 set_except_vector(8, handle_sys);
1762 set_except_vector(9, handle_bp);
1763 set_except_vector(10, rdhwr_noopt ? handle_ri :
1764 (cpu_has_vtag_icache ?
1765 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1766 set_except_vector(11, handle_cpu);
1767 set_except_vector(12, handle_ov);
1768 set_except_vector(13, handle_tr);
1769
1770 if (current_cpu_type() == CPU_R6000 ||
1771 current_cpu_type() == CPU_R6000A) {
1772 /*
1773 * The R6000 is the only R-series CPU that features a machine
1774 * check exception (similar to the R4000 cache error) and
1775 * unaligned ldc1/sdc1 exception. The handlers have not been
1776 * written yet. Well, anyway there is no R6000 machine on the
1777 * current list of targets for Linux/MIPS.
1778 * (Duh, crap, there is someone with a triple R6k machine)
1779 */
1780 //set_except_vector(14, handle_mc);
1781 //set_except_vector(15, handle_ndc);
1782 }
1783
1784
1785 if (board_nmi_handler_setup)
1786 board_nmi_handler_setup();
1787
1788 if (cpu_has_fpu && !cpu_has_nofpuex)
1789 set_except_vector(15, handle_fpe);
1790
1791 set_except_vector(22, handle_mdmx);
1792
1793 if (cpu_has_mcheck)
1794 set_except_vector(24, handle_mcheck);
1795
1796 if (cpu_has_mipsmt)
1797 set_except_vector(25, handle_mt);
1798
1799 set_except_vector(26, handle_dsp);
1800
1801 if (cpu_has_vce)
1802 /* Special exception: R4[04]00 uses also the divec space. */
1803 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1804 else if (cpu_has_4kex)
1805 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1806 else
1807 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1808
1809 local_flush_icache_range(ebase, ebase + 0x400);
1810 flush_tlb_handlers();
1811
1812 sort_extable(__start___dbe_table, __stop___dbe_table);
1813
1814 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1815 }