arch/mips/pci/pci-xlr.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/pci.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/msi.h>
  40 #include <linux/mm.h>
  41 #include <linux/irq.h>
  42 #include <linux/irqdesc.h>
  43 #include <linux/console.h>
  44
  45 #include <asm/io.h>
  46
  47 #include <asm/netlogic/interrupt.h>
  48 #include <asm/netlogic/haldefs.h>
  49
  50 #include <asm/netlogic/xlr/msidef.h>
  51 #include <asm/netlogic/xlr/iomap.h>
  52 #include <asm/netlogic/xlr/pic.h>
  53 #include <asm/netlogic/xlr/xlr.h>
  54
  55 static void *pci_config_base;
  56
  57 #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
  58
  59 /* PCI ops */
  60 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
  61         int where)
  62 {
  63         u32 data;
  64         u32 *cfgaddr;
  65
  66         cfgaddr = (u32 *)(pci_config_base +
  67                         pci_cfg_addr(bus->number, devfn, where & ~3));
  68         data = *cfgaddr;
  69         return cpu_to_le32(data);
  70 }
  71
  72 static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
  73         int where, u32 data)
  74 {
  75         u32 *cfgaddr;
  76
  77         cfgaddr = (u32 *)(pci_config_base +
  78                         pci_cfg_addr(bus->number, devfn, where & ~3));
  79         *cfgaddr = cpu_to_le32(data);
  80 }
  81
  82 static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  83         int where, int size, u32 *val)
  84 {
  85         u32 data;
  86
  87         if ((size == 2) && (where & 1))
  88                 return PCIBIOS_BAD_REGISTER_NUMBER;
  89         else if ((size == 4) && (where & 3))
  90                 return PCIBIOS_BAD_REGISTER_NUMBER;
  91
  92         data = pci_cfg_read_32bit(bus, devfn, where);
  93
  94         if (size == 1)
  95                 *val = (data >> ((where & 3) << 3)) & 0xff;
  96         else if (size == 2)
  97                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  98         else
  99                 *val = data;
 100
 101         return PCIBIOS_SUCCESSFUL;
 102 }
 103
 104
 105 static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 106                 int where, int size, u32 val)
 107 {
 108         u32 data;
 109
 110         if ((size == 2) && (where & 1))
 111                 return PCIBIOS_BAD_REGISTER_NUMBER;
 112         else if ((size == 4) && (where & 3))
 113                 return PCIBIOS_BAD_REGISTER_NUMBER;
 114
 115         data = pci_cfg_read_32bit(bus, devfn, where);
 116
 117         if (size == 1)
 118                 data = (data & ~(0xff << ((where & 3) << 3))) |
 119                         (val << ((where & 3) << 3));
 120         else if (size == 2)
 121                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 122                         (val << ((where & 3) << 3));
 123         else
 124                 data = val;
 125
 126         pci_cfg_write_32bit(bus, devfn, where, data);
 127
 128         return PCIBIOS_SUCCESSFUL;
 129 }
 130
 131 struct pci_ops nlm_pci_ops = {
 132         .read  = nlm_pcibios_read,
 133         .write = nlm_pcibios_write
 134 };
 135
 136 static struct resource nlm_pci_mem_resource = {
 137         .name           = "XLR PCI MEM",
 138         .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
 139         .end            = 0xdfffffffUL,
 140         .flags          = IORESOURCE_MEM,
 141 };
 142
 143 static struct resource nlm_pci_io_resource = {
 144         .name           = "XLR IO MEM",
 145         .start          = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
 146         .end            = 0x100fffffUL,
 147         .flags          = IORESOURCE_IO,
 148 };
 149
 150 struct pci_controller nlm_pci_controller = {
 151         .index          = 0,
 152         .pci_ops        = &nlm_pci_ops,
 153         .mem_resource   = &nlm_pci_mem_resource,
 154         .mem_offset     = 0x00000000UL,
 155         .io_resource    = &nlm_pci_io_resource,
 156         .io_offset      = 0x00000000UL,
 157 };
 158
 159 static int get_irq_vector(const struct pci_dev *dev)
 160 {
 161         if (!nlm_chip_is_xls())
 162                 return  PIC_PCIX_IRQ;   /* for XLR just one IRQ*/
 163
 164         /*
 165          * For XLS PCIe, there is an IRQ per Link, find out which
 166          * link the device is on to assign interrupts
 167         */
 168         if (dev->bus->self == NULL)
 169                 return 0;
 170
 171         switch  (dev->bus->self->devfn) {
 172         case 0x0:
 173                 return PIC_PCIE_LINK0_IRQ;
 174         case 0x8:
 175                 return PIC_PCIE_LINK1_IRQ;
 176         case 0x10:
 177                 if (nlm_chip_is_xls_b())
 178                         return PIC_PCIE_XLSB0_LINK2_IRQ;
 179                 else
 180                         return PIC_PCIE_LINK2_IRQ;
 181         case 0x18:
 182                 if (nlm_chip_is_xls_b())
 183                         return PIC_PCIE_XLSB0_LINK3_IRQ;
 184                 else
 185                         return PIC_PCIE_LINK3_IRQ;
 186         }
 187         WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
 188         return 0;
 189 }
 190
 191 #ifdef CONFIG_PCI_MSI
 192 void destroy_irq(unsigned int irq)
 193 {
 194             /* nothing to do yet */
 195 }
 196
 197 void arch_teardown_msi_irq(unsigned int irq)
 198 {
 199         destroy_irq(irq);
 200 }
 201
 202 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
 203 {
 204         struct msi_msg msg;
 205         int irq, ret;
 206
 207         irq = get_irq_vector(dev);
 208         if (irq <= 0)
 209                 return 1;
 210
 211         msg.address_hi = MSI_ADDR_BASE_HI;
 212         msg.address_lo = MSI_ADDR_BASE_LO   |
 213                 MSI_ADDR_DEST_MODE_PHYSICAL |
 214                 MSI_ADDR_REDIRECTION_CPU;
 215
 216         msg.data = MSI_DATA_TRIGGER_EDGE |
 217                 MSI_DATA_LEVEL_ASSERT    |
 218                 MSI_DATA_DELIVERY_FIXED;
 219
 220         ret = irq_set_msi_desc(irq, desc);
 221         if (ret < 0) {
 222                 destroy_irq(irq);
 223                 return ret;
 224         }
 225
 226         write_msi_msg(irq, &msg);
 227         return 0;
 228 }
 229 #endif
 230
 231 /* Extra ACK needed for XLR on chip PCI controller */
 232 static void xlr_pci_ack(struct irq_data *d)
 233 {
 234         uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
 235
 236         nlm_read_reg(pcibase, (0x140 >> 2));
 237 }
 238
 239 /* Extra ACK needed for XLS on chip PCIe controller */
 240 static void xls_pcie_ack(struct irq_data *d)
 241 {
 242         uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
 243
 244         switch (d->irq) {
 245         case PIC_PCIE_LINK0_IRQ:
 246                 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
 247                 break;
 248         case PIC_PCIE_LINK1_IRQ:
 249                 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
 250                 break;
 251         case PIC_PCIE_LINK2_IRQ:
 252                 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
 253                 break;
 254         case PIC_PCIE_LINK3_IRQ:
 255                 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
 256                 break;
 257         }
 258 }
 259
 260 /* For XLS B silicon, the 3,4 PCI interrupts are different */
 261 static void xls_pcie_ack_b(struct irq_data *d)
 262 {
 263         uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
 264
 265         switch (d->irq) {
 266         case PIC_PCIE_LINK0_IRQ:
 267                 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
 268                 break;
 269         case PIC_PCIE_LINK1_IRQ:
 270                 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
 271                 break;
 272         case PIC_PCIE_XLSB0_LINK2_IRQ:
 273                 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
 274                 break;
 275         case PIC_PCIE_XLSB0_LINK3_IRQ:
 276                 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
 277                 break;
 278         }
 279 }
 280
 281 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 282 {
 283         return get_irq_vector(dev);
 284 }
 285
 286 /* Do platform specific device initialization at pci_enable_device() time */
 287 int pcibios_plat_dev_init(struct pci_dev *dev)
 288 {
 289         return 0;
 290 }
 291
 292 static int __init pcibios_init(void)
 293 {
 294         /* PSB assigns PCI resources */
 295         pci_probe_only = 1;
 296         pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 297
 298         /* Extend IO port for memory mapped io */
 299         ioport_resource.start =  0;
 300         ioport_resource.end   = ~0;
 301
 302         set_io_port_base(CKSEG1);
 303         nlm_pci_controller.io_map_base = CKSEG1;
 304
 305         pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
 306         register_pci_controller(&nlm_pci_controller);
 307
 308         /*
 309          * For PCI interrupts, we need to ack the PCI controller too, overload
 310          * irq handler data to do this
 311          */
 312         if (nlm_chip_is_xls()) {
 313                 if (nlm_chip_is_xls_b()) {
 314                         irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
 315                                                         xls_pcie_ack_b);
 316                         irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
 317                                                         xls_pcie_ack_b);
 318                         irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
 319                                                         xls_pcie_ack_b);
 320                         irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
 321                                                         xls_pcie_ack_b);
 322                 } else {
 323                         irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
 324                         irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
 325                         irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
 326                         irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
 327                 }
 328         } else {
 329                 /* XLR PCI controller ACK */
 330                 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
 331         }
 332
 333         return 0;
 334 }
 335
 336 arch_initcall(pcibios_init);
 337
 338 struct pci_fixup pcibios_fixups[] = {
 339         {0}
 340 };