spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / parisc / include / asm / psw.h
blob5a3e23c9ce639591549febc256f390363553fbcf
1 #ifndef _PARISC_PSW_H
4 #define PSW_I 0x00000001
5 #define PSW_D 0x00000002
6 #define PSW_P 0x00000004
7 #define PSW_Q 0x00000008
9 #define PSW_R 0x00000010
10 #define PSW_F 0x00000020
11 #define PSW_G 0x00000040 /* PA1.x only */
12 #define PSW_O 0x00000080 /* PA2.0 only */
14 /* ssm/rsm instructions number PSW_W and PSW_E differently */
15 #define PSW_SM_I PSW_I /* Enable External Interrupts */
16 #define PSW_SM_D PSW_D
17 #define PSW_SM_P PSW_P
18 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
19 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
20 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
22 #define PSW_SM_QUIET PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I
24 #define PSW_CB 0x0000ff00
26 #define PSW_M 0x00010000
27 #define PSW_V 0x00020000
28 #define PSW_C 0x00040000
29 #define PSW_B 0x00080000
31 #define PSW_X 0x00100000
32 #define PSW_N 0x00200000
33 #define PSW_L 0x00400000
34 #define PSW_H 0x00800000
36 #define PSW_T 0x01000000
37 #define PSW_S 0x02000000
38 #define PSW_E 0x04000000
39 #define PSW_W 0x08000000 /* PA2.0 only */
40 #define PSW_W_BIT 36 /* PA2.0 only */
42 #define PSW_Z 0x40000000 /* PA1.x only */
43 #define PSW_Y 0x80000000 /* PA1.x only */
45 #ifdef CONFIG_64BIT
46 # define PSW_HI_CB 0x000000ff /* PA2.0 only */
47 #endif
49 #ifdef CONFIG_64BIT
50 # define USER_PSW_HI_MASK PSW_HI_CB
51 # define WIDE_PSW PSW_W
52 #else
53 # define WIDE_PSW 0
54 #endif
56 /* Used when setting up for rfi */
57 #define KERNEL_PSW (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D)
58 #define REAL_MODE_PSW (WIDE_PSW | PSW_Q)
59 #define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
60 #define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
62 #endif