arch/sh/boards/board-sh7757lcr.c

   1 /*
   2  * Renesas R0P7757LC0012RL Support.
   3  *
   4  * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/gpio.h>
  14 #include <linux/irq.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/spi/flash.h>
  17 #include <linux/io.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/mmc/sh_mmcif.h>
  20 #include <linux/mmc/sh_mobile_sdhi.h>
  21 #include <linux/sh_eth.h>
  22 #include <linux/usb/renesas_usbhs.h>
  23 #include <cpu/sh7757.h>
  24 #include <asm/heartbeat.h>
  25
  26 static struct resource heartbeat_resource = {
  27         .start  = 0xffec005c,   /* PUDR */
  28         .end    = 0xffec005c,
  29         .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
  30 };
  31
  32 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
  33
  34 static struct heartbeat_data heartbeat_data = {
  35         .bit_pos        = heartbeat_bit_pos,
  36         .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
  37         .flags          = HEARTBEAT_INVERTED,
  38 };
  39
  40 static struct platform_device heartbeat_device = {
  41         .name           = "heartbeat",
  42         .id             = -1,
  43         .dev    = {
  44                 .platform_data  = &heartbeat_data,
  45         },
  46         .num_resources  = 1,
  47         .resource       = &heartbeat_resource,
  48 };
  49
  50 /* Fast Ethernet */
  51 #define GBECONT         0xffc10100
  52 #define GBECONT_RMII1   BIT(17)
  53 #define GBECONT_RMII0   BIT(16)
  54 static void sh7757_eth_set_mdio_gate(void *addr)
  55 {
  56         if (((unsigned long)addr & 0x00000fff) < 0x0800)
  57                 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
  58         else
  59                 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
  60 }
  61
  62 static struct resource sh_eth0_resources[] = {
  63         {
  64                 .start  = 0xfef00000,
  65                 .end    = 0xfef001ff,
  66                 .flags  = IORESOURCE_MEM,
  67         }, {
  68                 .start  = 84,
  69                 .end    = 84,
  70                 .flags  = IORESOURCE_IRQ,
  71         },
  72 };
  73
  74 static struct sh_eth_plat_data sh7757_eth0_pdata = {
  75         .phy = 1,
  76         .edmac_endian = EDMAC_LITTLE_ENDIAN,
  77         .register_type = SH_ETH_REG_FAST_SH4,
  78         .set_mdio_gate = sh7757_eth_set_mdio_gate,
  79 };
  80
  81 static struct platform_device sh7757_eth0_device = {
  82         .name           = "sh-eth",
  83         .resource       = sh_eth0_resources,
  84         .id             = 0,
  85         .num_resources  = ARRAY_SIZE(sh_eth0_resources),
  86         .dev            = {
  87                 .platform_data = &sh7757_eth0_pdata,
  88         },
  89 };
  90
  91 static struct resource sh_eth1_resources[] = {
  92         {
  93                 .start  = 0xfef00800,
  94                 .end    = 0xfef009ff,
  95                 .flags  = IORESOURCE_MEM,
  96         }, {
  97                 .start  = 84,
  98                 .end    = 84,
  99                 .flags  = IORESOURCE_IRQ,
 100         },
 101 };
 102
 103 static struct sh_eth_plat_data sh7757_eth1_pdata = {
 104         .phy = 1,
 105         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 106         .register_type = SH_ETH_REG_FAST_SH4,
 107         .set_mdio_gate = sh7757_eth_set_mdio_gate,
 108 };
 109
 110 static struct platform_device sh7757_eth1_device = {
 111         .name           = "sh-eth",
 112         .resource       = sh_eth1_resources,
 113         .id             = 1,
 114         .num_resources  = ARRAY_SIZE(sh_eth1_resources),
 115         .dev            = {
 116                 .platform_data = &sh7757_eth1_pdata,
 117         },
 118 };
 119
 120 static void sh7757_eth_giga_set_mdio_gate(void *addr)
 121 {
 122         if (((unsigned long)addr & 0x00000fff) < 0x0800) {
 123                 gpio_set_value(GPIO_PTT4, 1);
 124                 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
 125         } else {
 126                 gpio_set_value(GPIO_PTT4, 0);
 127                 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
 128         }
 129 }
 130
 131 static struct resource sh_eth_giga0_resources[] = {
 132         {
 133                 .start  = 0xfee00000,
 134                 .end    = 0xfee007ff,
 135                 .flags  = IORESOURCE_MEM,
 136         }, {
 137                 /* TSU */
 138                 .start  = 0xfee01800,
 139                 .end    = 0xfee01fff,
 140                 .flags  = IORESOURCE_MEM,
 141         }, {
 142                 .start  = 315,
 143                 .end    = 315,
 144                 .flags  = IORESOURCE_IRQ,
 145         },
 146 };
 147
 148 static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
 149         .phy = 18,
 150         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 151         .register_type = SH_ETH_REG_GIGABIT,
 152         .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
 153         .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
 154 };
 155
 156 static struct platform_device sh7757_eth_giga0_device = {
 157         .name           = "sh-eth",
 158         .resource       = sh_eth_giga0_resources,
 159         .id             = 2,
 160         .num_resources  = ARRAY_SIZE(sh_eth_giga0_resources),
 161         .dev            = {
 162                 .platform_data = &sh7757_eth_giga0_pdata,
 163         },
 164 };
 165
 166 static struct resource sh_eth_giga1_resources[] = {
 167         {
 168                 .start  = 0xfee00800,
 169                 .end    = 0xfee00fff,
 170                 .flags  = IORESOURCE_MEM,
 171         }, {
 172                 /* TSU */
 173                 .start  = 0xfee01800,
 174                 .end    = 0xfee01fff,
 175                 .flags  = IORESOURCE_MEM,
 176         }, {
 177                 .start  = 316,
 178                 .end    = 316,
 179                 .flags  = IORESOURCE_IRQ,
 180         },
 181 };
 182
 183 static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
 184         .phy = 19,
 185         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 186         .register_type = SH_ETH_REG_GIGABIT,
 187         .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
 188         .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
 189 };
 190
 191 static struct platform_device sh7757_eth_giga1_device = {
 192         .name           = "sh-eth",
 193         .resource       = sh_eth_giga1_resources,
 194         .id             = 3,
 195         .num_resources  = ARRAY_SIZE(sh_eth_giga1_resources),
 196         .dev            = {
 197                 .platform_data = &sh7757_eth_giga1_pdata,
 198         },
 199 };
 200
 201 /* SH_MMCIF */
 202 static struct resource sh_mmcif_resources[] = {
 203         [0] = {
 204                 .start  = 0xffcb0000,
 205                 .end    = 0xffcb00ff,
 206                 .flags  = IORESOURCE_MEM,
 207         },
 208         [1] = {
 209                 .start  = 211,
 210                 .flags  = IORESOURCE_IRQ,
 211         },
 212         [2] = {
 213                 .start  = 212,
 214                 .flags  = IORESOURCE_IRQ,
 215         },
 216 };
 217
 218 static struct sh_mmcif_plat_data sh_mmcif_plat = {
 219         .sup_pclk       = 0x0f,
 220         .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
 221                           MMC_CAP_NONREMOVABLE,
 222         .ocr            = MMC_VDD_32_33 | MMC_VDD_33_34,
 223         .slave_id_tx    = SHDMA_SLAVE_MMCIF_TX,
 224         .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
 225 };
 226
 227 static struct platform_device sh_mmcif_device = {
 228         .name           = "sh_mmcif",
 229         .id             = 0,
 230         .dev            = {
 231                 .platform_data          = &sh_mmcif_plat,
 232         },
 233         .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
 234         .resource       = sh_mmcif_resources,
 235 };
 236
 237 /* SDHI0 */
 238 static struct sh_mobile_sdhi_info sdhi_info = {
 239         .dma_slave_tx   = SHDMA_SLAVE_SDHI_TX,
 240         .dma_slave_rx   = SHDMA_SLAVE_SDHI_RX,
 241         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
 242 };
 243
 244 static struct resource sdhi_resources[] = {
 245         [0] = {
 246                 .start  = 0xffe50000,
 247                 .end    = 0xffe501ff,
 248                 .flags  = IORESOURCE_MEM,
 249         },
 250         [1] = {
 251                 .start  = 20,
 252                 .flags  = IORESOURCE_IRQ,
 253         },
 254 };
 255
 256 static struct platform_device sdhi_device = {
 257         .name           = "sh_mobile_sdhi",
 258         .num_resources  = ARRAY_SIZE(sdhi_resources),
 259         .resource       = sdhi_resources,
 260         .id             = 0,
 261         .dev    = {
 262                 .platform_data  = &sdhi_info,
 263         },
 264 };
 265
 266 static int usbhs0_get_id(struct platform_device *pdev)
 267 {
 268         return USBHS_GADGET;
 269 }
 270
 271 static struct renesas_usbhs_platform_info usb0_data = {
 272         .platform_callback = {
 273                 .get_id = usbhs0_get_id,
 274         },
 275         .driver_param = {
 276                 .buswait_bwait = 5,
 277         }
 278 };
 279
 280 static struct resource usb0_resources[] = {
 281         [0] = {
 282                 .start  = 0xfe450000,
 283                 .end    = 0xfe4501ff,
 284                 .flags  = IORESOURCE_MEM,
 285         },
 286         [1] = {
 287                 .start  = 50,
 288                 .end    = 50,
 289                 .flags  = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 static struct platform_device usb0_device = {
 294         .name           = "renesas_usbhs",
 295         .id             = 0,
 296         .dev = {
 297                 .platform_data          = &usb0_data,
 298         },
 299         .num_resources  = ARRAY_SIZE(usb0_resources),
 300         .resource       = usb0_resources,
 301 };
 302
 303 static struct platform_device *sh7757lcr_devices[] __initdata = {
 304         &heartbeat_device,
 305         &sh7757_eth0_device,
 306         &sh7757_eth1_device,
 307         &sh7757_eth_giga0_device,
 308         &sh7757_eth_giga1_device,
 309         &sh_mmcif_device,
 310         &sdhi_device,
 311         &usb0_device,
 312 };
 313
 314 static struct flash_platform_data spi_flash_data = {
 315         .name = "m25p80",
 316         .type = "m25px64",
 317 };
 318
 319 static struct spi_board_info spi_board_info[] = {
 320         {
 321                 .modalias = "m25p80",
 322                 .max_speed_hz = 25000000,
 323                 .bus_num = 0,
 324                 .chip_select = 1,
 325                 .platform_data = &spi_flash_data,
 326         },
 327 };
 328
 329 static int __init sh7757lcr_devices_setup(void)
 330 {
 331         /* RGMII (PTA) */
 332         gpio_request(GPIO_FN_ET0_MDC, NULL);
 333         gpio_request(GPIO_FN_ET0_MDIO, NULL);
 334         gpio_request(GPIO_FN_ET1_MDC, NULL);
 335         gpio_request(GPIO_FN_ET1_MDIO, NULL);
 336
 337         /* ONFI (PTB, PTZ) */
 338         gpio_request(GPIO_FN_ON_NRE, NULL);
 339         gpio_request(GPIO_FN_ON_NWE, NULL);
 340         gpio_request(GPIO_FN_ON_NWP, NULL);
 341         gpio_request(GPIO_FN_ON_NCE0, NULL);
 342         gpio_request(GPIO_FN_ON_R_B0, NULL);
 343         gpio_request(GPIO_FN_ON_ALE, NULL);
 344         gpio_request(GPIO_FN_ON_CLE, NULL);
 345
 346         gpio_request(GPIO_FN_ON_DQ7, NULL);
 347         gpio_request(GPIO_FN_ON_DQ6, NULL);
 348         gpio_request(GPIO_FN_ON_DQ5, NULL);
 349         gpio_request(GPIO_FN_ON_DQ4, NULL);
 350         gpio_request(GPIO_FN_ON_DQ3, NULL);
 351         gpio_request(GPIO_FN_ON_DQ2, NULL);
 352         gpio_request(GPIO_FN_ON_DQ1, NULL);
 353         gpio_request(GPIO_FN_ON_DQ0, NULL);
 354
 355         /* IRQ8 to 0 (PTB, PTC) */
 356         gpio_request(GPIO_FN_IRQ8, NULL);
 357         gpio_request(GPIO_FN_IRQ7, NULL);
 358         gpio_request(GPIO_FN_IRQ6, NULL);
 359         gpio_request(GPIO_FN_IRQ5, NULL);
 360         gpio_request(GPIO_FN_IRQ4, NULL);
 361         gpio_request(GPIO_FN_IRQ3, NULL);
 362         gpio_request(GPIO_FN_IRQ2, NULL);
 363         gpio_request(GPIO_FN_IRQ1, NULL);
 364         gpio_request(GPIO_FN_IRQ0, NULL);
 365
 366         /* SPI0 (PTD) */
 367         gpio_request(GPIO_FN_SP0_MOSI, NULL);
 368         gpio_request(GPIO_FN_SP0_MISO, NULL);
 369         gpio_request(GPIO_FN_SP0_SCK, NULL);
 370         gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
 371         gpio_request(GPIO_FN_SP0_SS0, NULL);
 372         gpio_request(GPIO_FN_SP0_SS1, NULL);
 373         gpio_request(GPIO_FN_SP0_SS2, NULL);
 374         gpio_request(GPIO_FN_SP0_SS3, NULL);
 375
 376         /* RMII 0/1 (PTE, PTF) */
 377         gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
 378         gpio_request(GPIO_FN_RMII0_TXD1, NULL);
 379         gpio_request(GPIO_FN_RMII0_TXD0, NULL);
 380         gpio_request(GPIO_FN_RMII0_TXEN, NULL);
 381         gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
 382         gpio_request(GPIO_FN_RMII0_RXD1, NULL);
 383         gpio_request(GPIO_FN_RMII0_RXD0, NULL);
 384         gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
 385         gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
 386         gpio_request(GPIO_FN_RMII1_TXD1, NULL);
 387         gpio_request(GPIO_FN_RMII1_TXD0, NULL);
 388         gpio_request(GPIO_FN_RMII1_TXEN, NULL);
 389         gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
 390         gpio_request(GPIO_FN_RMII1_RXD1, NULL);
 391         gpio_request(GPIO_FN_RMII1_RXD0, NULL);
 392         gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
 393
 394         /* eMMC (PTG) */
 395         gpio_request(GPIO_FN_MMCCLK, NULL);
 396         gpio_request(GPIO_FN_MMCCMD, NULL);
 397         gpio_request(GPIO_FN_MMCDAT7, NULL);
 398         gpio_request(GPIO_FN_MMCDAT6, NULL);
 399         gpio_request(GPIO_FN_MMCDAT5, NULL);
 400         gpio_request(GPIO_FN_MMCDAT4, NULL);
 401         gpio_request(GPIO_FN_MMCDAT3, NULL);
 402         gpio_request(GPIO_FN_MMCDAT2, NULL);
 403         gpio_request(GPIO_FN_MMCDAT1, NULL);
 404         gpio_request(GPIO_FN_MMCDAT0, NULL);
 405
 406         /* LPC (PTG, PTH, PTQ, PTU) */
 407         gpio_request(GPIO_FN_SERIRQ, NULL);
 408         gpio_request(GPIO_FN_LPCPD, NULL);
 409         gpio_request(GPIO_FN_LDRQ, NULL);
 410         gpio_request(GPIO_FN_WP, NULL);
 411         gpio_request(GPIO_FN_FMS0, NULL);
 412         gpio_request(GPIO_FN_LAD3, NULL);
 413         gpio_request(GPIO_FN_LAD2, NULL);
 414         gpio_request(GPIO_FN_LAD1, NULL);
 415         gpio_request(GPIO_FN_LAD0, NULL);
 416         gpio_request(GPIO_FN_LFRAME, NULL);
 417         gpio_request(GPIO_FN_LRESET, NULL);
 418         gpio_request(GPIO_FN_LCLK, NULL);
 419         gpio_request(GPIO_FN_LGPIO7, NULL);
 420         gpio_request(GPIO_FN_LGPIO6, NULL);
 421         gpio_request(GPIO_FN_LGPIO5, NULL);
 422         gpio_request(GPIO_FN_LGPIO4, NULL);
 423
 424         /* SPI1 (PTH) */
 425         gpio_request(GPIO_FN_SP1_MOSI, NULL);
 426         gpio_request(GPIO_FN_SP1_MISO, NULL);
 427         gpio_request(GPIO_FN_SP1_SCK, NULL);
 428         gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
 429         gpio_request(GPIO_FN_SP1_SS0, NULL);
 430         gpio_request(GPIO_FN_SP1_SS1, NULL);
 431
 432         /* SDHI (PTI) */
 433         gpio_request(GPIO_FN_SD_WP, NULL);
 434         gpio_request(GPIO_FN_SD_CD, NULL);
 435         gpio_request(GPIO_FN_SD_CLK, NULL);
 436         gpio_request(GPIO_FN_SD_CMD, NULL);
 437         gpio_request(GPIO_FN_SD_D3, NULL);
 438         gpio_request(GPIO_FN_SD_D2, NULL);
 439         gpio_request(GPIO_FN_SD_D1, NULL);
 440         gpio_request(GPIO_FN_SD_D0, NULL);
 441
 442         /* SCIF3/4 (PTJ, PTW) */
 443         gpio_request(GPIO_FN_RTS3, NULL);
 444         gpio_request(GPIO_FN_CTS3, NULL);
 445         gpio_request(GPIO_FN_TXD3, NULL);
 446         gpio_request(GPIO_FN_RXD3, NULL);
 447         gpio_request(GPIO_FN_RTS4, NULL);
 448         gpio_request(GPIO_FN_RXD4, NULL);
 449         gpio_request(GPIO_FN_TXD4, NULL);
 450         gpio_request(GPIO_FN_CTS4, NULL);
 451
 452         /* SERMUX (PTK, PTL, PTO, PTV) */
 453         gpio_request(GPIO_FN_COM2_TXD, NULL);
 454         gpio_request(GPIO_FN_COM2_RXD, NULL);
 455         gpio_request(GPIO_FN_COM2_RTS, NULL);
 456         gpio_request(GPIO_FN_COM2_CTS, NULL);
 457         gpio_request(GPIO_FN_COM2_DTR, NULL);
 458         gpio_request(GPIO_FN_COM2_DSR, NULL);
 459         gpio_request(GPIO_FN_COM2_DCD, NULL);
 460         gpio_request(GPIO_FN_COM2_RI, NULL);
 461         gpio_request(GPIO_FN_RAC_RXD, NULL);
 462         gpio_request(GPIO_FN_RAC_RTS, NULL);
 463         gpio_request(GPIO_FN_RAC_CTS, NULL);
 464         gpio_request(GPIO_FN_RAC_DTR, NULL);
 465         gpio_request(GPIO_FN_RAC_DSR, NULL);
 466         gpio_request(GPIO_FN_RAC_DCD, NULL);
 467         gpio_request(GPIO_FN_RAC_TXD, NULL);
 468         gpio_request(GPIO_FN_COM1_TXD, NULL);
 469         gpio_request(GPIO_FN_COM1_RXD, NULL);
 470         gpio_request(GPIO_FN_COM1_RTS, NULL);
 471         gpio_request(GPIO_FN_COM1_CTS, NULL);
 472
 473         writeb(0x10, 0xfe470000);       /* SMR0: SerMux mode 0 */
 474
 475         /* IIC (PTM, PTR, PTS) */
 476         gpio_request(GPIO_FN_SDA7, NULL);
 477         gpio_request(GPIO_FN_SCL7, NULL);
 478         gpio_request(GPIO_FN_SDA6, NULL);
 479         gpio_request(GPIO_FN_SCL6, NULL);
 480         gpio_request(GPIO_FN_SDA5, NULL);
 481         gpio_request(GPIO_FN_SCL5, NULL);
 482         gpio_request(GPIO_FN_SDA4, NULL);
 483         gpio_request(GPIO_FN_SCL4, NULL);
 484         gpio_request(GPIO_FN_SDA3, NULL);
 485         gpio_request(GPIO_FN_SCL3, NULL);
 486         gpio_request(GPIO_FN_SDA2, NULL);
 487         gpio_request(GPIO_FN_SCL2, NULL);
 488         gpio_request(GPIO_FN_SDA1, NULL);
 489         gpio_request(GPIO_FN_SCL1, NULL);
 490         gpio_request(GPIO_FN_SDA0, NULL);
 491         gpio_request(GPIO_FN_SCL0, NULL);
 492
 493         /* USB (PTN) */
 494         gpio_request(GPIO_FN_VBUS_EN, NULL);
 495         gpio_request(GPIO_FN_VBUS_OC, NULL);
 496
 497         /* SGPIO1/0 (PTN, PTO) */
 498         gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
 499         gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
 500         gpio_request(GPIO_FN_SGPIO1_DI, NULL);
 501         gpio_request(GPIO_FN_SGPIO1_DO, NULL);
 502         gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
 503         gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
 504         gpio_request(GPIO_FN_SGPIO0_DI, NULL);
 505         gpio_request(GPIO_FN_SGPIO0_DO, NULL);
 506
 507         /* WDT (PTN) */
 508         gpio_request(GPIO_FN_SUB_CLKIN, NULL);
 509
 510         /* System (PTT) */
 511         gpio_request(GPIO_FN_STATUS1, NULL);
 512         gpio_request(GPIO_FN_STATUS0, NULL);
 513
 514         /* PWMX (PTT) */
 515         gpio_request(GPIO_FN_PWMX1, NULL);
 516         gpio_request(GPIO_FN_PWMX0, NULL);
 517
 518         /* R-SPI (PTV) */
 519         gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
 520         gpio_request(GPIO_FN_R_SPI_MISO, NULL);
 521         gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
 522         gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
 523         gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
 524
 525         /* EVC (PTV, PTW) */
 526         gpio_request(GPIO_FN_EVENT7, NULL);
 527         gpio_request(GPIO_FN_EVENT6, NULL);
 528         gpio_request(GPIO_FN_EVENT5, NULL);
 529         gpio_request(GPIO_FN_EVENT4, NULL);
 530         gpio_request(GPIO_FN_EVENT3, NULL);
 531         gpio_request(GPIO_FN_EVENT2, NULL);
 532         gpio_request(GPIO_FN_EVENT1, NULL);
 533         gpio_request(GPIO_FN_EVENT0, NULL);
 534
 535         /* LED for heartbeat */
 536         gpio_request(GPIO_PTU3, NULL);
 537         gpio_direction_output(GPIO_PTU3, 1);
 538         gpio_request(GPIO_PTU2, NULL);
 539         gpio_direction_output(GPIO_PTU2, 1);
 540         gpio_request(GPIO_PTU1, NULL);
 541         gpio_direction_output(GPIO_PTU1, 1);
 542         gpio_request(GPIO_PTU0, NULL);
 543         gpio_direction_output(GPIO_PTU0, 1);
 544
 545         /* control for MDIO of Gigabit Ethernet */
 546         gpio_request(GPIO_PTT4, NULL);
 547         gpio_direction_output(GPIO_PTT4, 1);
 548
 549         /* control for eMMC */
 550         gpio_request(GPIO_PTT7, NULL);          /* eMMC_RST# */
 551         gpio_direction_output(GPIO_PTT7, 0);
 552         gpio_request(GPIO_PTT6, NULL);          /* eMMC_INDEX# */
 553         gpio_direction_output(GPIO_PTT6, 0);
 554         gpio_request(GPIO_PTT5, NULL);          /* eMMC_PRST# */
 555         gpio_direction_output(GPIO_PTT5, 1);
 556
 557         /* register SPI device information */
 558         spi_register_board_info(spi_board_info,
 559                                 ARRAY_SIZE(spi_board_info));
 560
 561         /* General platform */
 562         return platform_add_devices(sh7757lcr_devices,
 563                                     ARRAY_SIZE(sh7757lcr_devices));
 564 }
 565 arch_initcall(sh7757lcr_devices_setup);
 566
 567 /* Initialize IRQ setting */
 568 void __init init_sh7757lcr_IRQ(void)
 569 {
 570         plat_irq_setup_pins(IRQ_MODE_IRQ7654);
 571         plat_irq_setup_pins(IRQ_MODE_IRQ3210);
 572 }
 573
 574 /* Initialize the board */
 575 static void __init sh7757lcr_setup(char **cmdline_p)
 576 {
 577         printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
 578 }
 579
 580 static int sh7757lcr_mode_pins(void)
 581 {
 582         int value = 0;
 583
 584         /* These are the factory default settings of S3 (Low active).
 585          * If you change these dip switches then you will need to
 586          * adjust the values below as well.
 587          */
 588         value |= MODE_PIN0;     /* Clock Mode: 1 */
 589
 590         return value;
 591 }
 592
 593 /* The Machine Vector */
 594 static struct sh_machine_vector mv_sh7757lcr __initmv = {
 595         .mv_name                = "SH7757LCR",
 596         .mv_setup               = sh7757lcr_setup,
 597         .mv_init_irq            = init_sh7757lcr_IRQ,
 598         .mv_mode_pins           = sh7757lcr_mode_pins,
 599 };
 600