spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / sh / include / asm / auxvec.h
blob483effd65e004bfadbea95c0da0c96d28716db72
1 #ifndef __ASM_SH_AUXVEC_H
2 #define __ASM_SH_AUXVEC_H
4 /*
5 * Architecture-neutral AT_ values in 0-17, leave some room
6 * for more of them.
7 */
9 /*
10 * This entry gives some information about the FPU initialization
11 * performed by the kernel.
13 #define AT_FPUCW 18 /* Used FPU control word. */
15 #if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__)
17 * Only define this in the vsyscall case, the entry point to
18 * the vsyscall page gets placed here. The kernel will attempt
19 * to build a gate VMA we don't care about otherwise..
21 #define AT_SYSINFO_EHDR 33
22 #endif
25 * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
26 * value is -1, then the cache doesn't exist. Otherwise:
28 * bit 0-3: Cache set-associativity; 0 means fully associative.
29 * bit 4-7: Log2 of cacheline size.
30 * bit 8-31: Size of the entire cache >> 8.
32 #define AT_L1I_CACHESHAPE 34
33 #define AT_L1D_CACHESHAPE 35
34 #define AT_L2_CACHESHAPE 36
36 #endif /* __ASM_SH_AUXVEC_H */