spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / sh / include / asm / mmu_context_32.h
blob10e2e17210d28592d1c9a1c7fdc92b4cc2679235
1 #ifndef __ASM_SH_MMU_CONTEXT_32_H
2 #define __ASM_SH_MMU_CONTEXT_32_H
4 /*
5 * Destroy context related info for an mm_struct that is about
6 * to be put to rest.
7 */
8 static inline void destroy_context(struct mm_struct *mm)
10 /* Do nothing */
13 #ifdef CONFIG_CPU_HAS_PTEAEX
14 static inline void set_asid(unsigned long asid)
16 __raw_writel(asid, MMU_PTEAEX);
19 static inline unsigned long get_asid(void)
21 return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK;
23 #else
24 static inline void set_asid(unsigned long asid)
26 unsigned long __dummy;
28 __asm__ __volatile__ ("mov.l %2, %0\n\t"
29 "and %3, %0\n\t"
30 "or %1, %0\n\t"
31 "mov.l %0, %2"
32 : "=&r" (__dummy)
33 : "r" (asid), "m" (__m(MMU_PTEH)),
34 "r" (0xffffff00));
37 static inline unsigned long get_asid(void)
39 unsigned long asid;
41 __asm__ __volatile__ ("mov.l %1, %0"
42 : "=r" (asid)
43 : "m" (__m(MMU_PTEH)));
44 asid &= MMU_CONTEXT_ASID_MASK;
45 return asid;
47 #endif /* CONFIG_CPU_HAS_PTEAEX */
49 /* MMU_TTB is used for optimizing the fault handling. */
50 static inline void set_TTB(pgd_t *pgd)
52 __raw_writel((unsigned long)pgd, MMU_TTB);
55 static inline pgd_t *get_TTB(void)
57 return (pgd_t *)__raw_readl(MMU_TTB);
59 #endif /* __ASM_SH_MMU_CONTEXT_32_H */