arch/sh/include/cpu-sh5/cpu/registers.h

   1 #ifndef __ASM_SH_CPU_SH5_REGISTERS_H
   2 #define __ASM_SH_CPU_SH5_REGISTERS_H
   3
   4 /*
   5  * include/asm-sh/cpu-sh5/registers.h
   6  *
   7  * Copyright (C) 2000, 2001  Paolo Alberelli
   8  * Copyright (C) 2004  Richard Curnow
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14
  15 #ifdef __ASSEMBLY__
  16 /* =====================================================================
  17 **
  18 ** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
  19 **            Assigns symbolic names to control & target registers.
  20 */
  21
  22 /*
  23  * Define some useful aliases for control registers.
  24  */
  25 #define SR      cr0
  26 #define SSR     cr1
  27 #define PSSR    cr2
  28                         /* cr3 UNDEFINED */
  29 #define INTEVT  cr4
  30 #define EXPEVT  cr5
  31 #define PEXPEVT cr6
  32 #define TRA     cr7
  33 #define SPC     cr8
  34 #define PSPC    cr9
  35 #define RESVEC  cr10
  36 #define VBR     cr11
  37                         /* cr12 UNDEFINED */
  38 #define TEA     cr13
  39                         /* cr14-cr15 UNDEFINED */
  40 #define DCR     cr16
  41 #define KCR0    cr17
  42 #define KCR1    cr18
  43                         /* cr19-cr31 UNDEFINED */
  44                         /* cr32-cr61 RESERVED */
  45 #define CTC     cr62
  46 #define USR     cr63
  47
  48 /*
  49  * ABI dependent registers (general purpose set)
  50  */
  51 #define RET     r2
  52 #define ARG1    r2
  53 #define ARG2    r3
  54 #define ARG3    r4
  55 #define ARG4    r5
  56 #define ARG5    r6
  57 #define ARG6    r7
  58 #define SP      r15
  59 #define LINK    r18
  60 #define ZERO    r63
  61
  62 /*
  63  * Status register defines: used only by assembly sources (and
  64  *                          syntax independednt)
  65  */
  66 #define SR_RESET_VAL    0x0000000050008000
  67 #define SR_HARMLESS     0x00000000500080f0      /* Write ignores for most */
  68 #define SR_ENABLE_FPU   0xffffffffffff7fff      /* AND with this */
  69
  70 #if defined (CONFIG_SH64_SR_WATCH)
  71 #define SR_ENABLE_MMU   0x0000000084000000      /* OR with this */
  72 #else
  73 #define SR_ENABLE_MMU   0x0000000080000000      /* OR with this */
  74 #endif
  75
  76 #define SR_UNBLOCK_EXC  0xffffffffefffffff      /* AND with this */
  77 #define SR_BLOCK_EXC    0x0000000010000000      /* OR with this */
  78
  79 #else   /* Not __ASSEMBLY__ syntax */
  80
  81 /*
  82 ** Stringify reg. name
  83 */
  84 #define __str(x)  #x
  85
  86 /* Stringify control register names for use in inline assembly */
  87 #define __SR __str(SR)
  88 #define __SSR __str(SSR)
  89 #define __PSSR __str(PSSR)
  90 #define __INTEVT __str(INTEVT)
  91 #define __EXPEVT __str(EXPEVT)
  92 #define __PEXPEVT __str(PEXPEVT)
  93 #define __TRA __str(TRA)
  94 #define __SPC __str(SPC)
  95 #define __PSPC __str(PSPC)
  96 #define __RESVEC __str(RESVEC)
  97 #define __VBR __str(VBR)
  98 #define __TEA __str(TEA)
  99 #define __DCR __str(DCR)
 100 #define __KCR0 __str(KCR0)
 101 #define __KCR1 __str(KCR1)
 102 #define __CTC __str(CTC)
 103 #define __USR __str(USR)
 104
 105 #endif /* __ASSEMBLY__ */
 106 #endif /* __ASM_SH_CPU_SH5_REGISTERS_H */