arch/sh/kernel/cpu/sh2/setup-sh7619.c

   1 /*
   2  * SH7619 Setup
   3  *
   4  *  Copyright (C) 2006  Yoshinori Sato
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17
  18 enum {
  19         UNUSED = 0,
  20
  21         /* interrupt sources */
  22         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  23         WDT, EDMAC, CMT0, CMT1,
  24         SCIF0, SCIF1, SCIF2,
  25         HIF_HIFI, HIF_HIFBI,
  26         DMAC0, DMAC1, DMAC2, DMAC3,
  27         SIOF,
  28 };
  29
  30 static struct intc_vect vectors[] __initdata = {
  31         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  32         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  33         INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
  34         INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
  35         INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
  36         INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
  37         INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
  38         INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
  39         INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
  40         INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
  41         INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
  42         INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
  43         INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
  44         INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
  45         INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
  46         INTC_IRQ(SIOF, 108),
  47 };
  48
  49 static struct intc_prio_reg prio_registers[] __initdata = {
  50         { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
  51         { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
  52         { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
  53         { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
  54         { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
  55         { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
  56         { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
  57 };
  58
  59 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
  60                          NULL, prio_registers, NULL);
  61
  62 static struct plat_sci_port scif0_platform_data = {
  63         .mapbase        = 0xf8400000,
  64         .flags          = UPF_BOOT_AUTOCONF,
  65         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  66         .scbrr_algo_id  = SCBRR_ALGO_2,
  67         .type           = PORT_SCIF,
  68         .irqs           = { 88, 88, 88, 88 },
  69 };
  70
  71 static struct platform_device scif0_device = {
  72         .name           = "sh-sci",
  73         .id             = 0,
  74         .dev            = {
  75                 .platform_data  = &scif0_platform_data,
  76         },
  77 };
  78
  79 static struct plat_sci_port scif1_platform_data = {
  80         .mapbase        = 0xf8410000,
  81         .flags          = UPF_BOOT_AUTOCONF,
  82         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  83         .scbrr_algo_id  = SCBRR_ALGO_2,
  84         .type           = PORT_SCIF,
  85         .irqs           = { 92, 92, 92, 92 },
  86 };
  87
  88 static struct platform_device scif1_device = {
  89         .name           = "sh-sci",
  90         .id             = 1,
  91         .dev            = {
  92                 .platform_data  = &scif1_platform_data,
  93         },
  94 };
  95
  96 static struct plat_sci_port scif2_platform_data = {
  97         .mapbase        = 0xf8420000,
  98         .flags          = UPF_BOOT_AUTOCONF,
  99         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 100         .scbrr_algo_id  = SCBRR_ALGO_2,
 101         .type           = PORT_SCIF,
 102         .irqs           = { 96, 96, 96, 96 },
 103 };
 104
 105 static struct platform_device scif2_device = {
 106         .name           = "sh-sci",
 107         .id             = 2,
 108         .dev            = {
 109                 .platform_data  = &scif2_platform_data,
 110         },
 111 };
 112
 113 static struct resource eth_resources[] = {
 114         [0] = {
 115                 .start = 0xfb000000,
 116                 .end =   0xfb0001c8,
 117                 .flags = IORESOURCE_MEM,
 118         },
 119         [1] = {
 120                 .start = 85,
 121                 .end = 85,
 122                 .flags = IORESOURCE_IRQ,
 123         },
 124 };
 125
 126 static struct platform_device eth_device = {
 127         .name = "sh-eth",
 128         .id     = -1,
 129         .dev = {
 130                 .platform_data = (void *)1,
 131         },
 132         .num_resources = ARRAY_SIZE(eth_resources),
 133         .resource = eth_resources,
 134 };
 135
 136 static struct sh_timer_config cmt0_platform_data = {
 137         .channel_offset = 0x02,
 138         .timer_bit = 0,
 139         .clockevent_rating = 125,
 140         .clocksource_rating = 0, /* disabled due to code generation issues */
 141 };
 142
 143 static struct resource cmt0_resources[] = {
 144         [0] = {
 145                 .start  = 0xf84a0072,
 146                 .end    = 0xf84a0077,
 147                 .flags  = IORESOURCE_MEM,
 148         },
 149         [1] = {
 150                 .start  = 86,
 151                 .flags  = IORESOURCE_IRQ,
 152         },
 153 };
 154
 155 static struct platform_device cmt0_device = {
 156         .name           = "sh_cmt",
 157         .id             = 0,
 158         .dev = {
 159                 .platform_data  = &cmt0_platform_data,
 160         },
 161         .resource       = cmt0_resources,
 162         .num_resources  = ARRAY_SIZE(cmt0_resources),
 163 };
 164
 165 static struct sh_timer_config cmt1_platform_data = {
 166         .channel_offset = 0x08,
 167         .timer_bit = 1,
 168         .clockevent_rating = 125,
 169         .clocksource_rating = 0, /* disabled due to code generation issues */
 170 };
 171
 172 static struct resource cmt1_resources[] = {
 173         [0] = {
 174                 .start  = 0xf84a0078,
 175                 .end    = 0xf84a007d,
 176                 .flags  = IORESOURCE_MEM,
 177         },
 178         [1] = {
 179                 .start  = 87,
 180                 .flags  = IORESOURCE_IRQ,
 181         },
 182 };
 183
 184 static struct platform_device cmt1_device = {
 185         .name           = "sh_cmt",
 186         .id             = 1,
 187         .dev = {
 188                 .platform_data  = &cmt1_platform_data,
 189         },
 190         .resource       = cmt1_resources,
 191         .num_resources  = ARRAY_SIZE(cmt1_resources),
 192 };
 193
 194 static struct platform_device *sh7619_devices[] __initdata = {
 195         &scif0_device,
 196         &scif1_device,
 197         &scif2_device,
 198         &eth_device,
 199         &cmt0_device,
 200         &cmt1_device,
 201 };
 202
 203 static int __init sh7619_devices_setup(void)
 204 {
 205         return platform_add_devices(sh7619_devices,
 206                                     ARRAY_SIZE(sh7619_devices));
 207 }
 208 arch_initcall(sh7619_devices_setup);
 209
 210 void __init plat_irq_setup(void)
 211 {
 212         register_intc_controller(&intc_desc);
 213 }
 214
 215 static struct platform_device *sh7619_early_devices[] __initdata = {
 216         &scif0_device,
 217         &scif1_device,
 218         &scif2_device,
 219         &cmt0_device,
 220         &cmt1_device,
 221 };
 222
 223 #define STBCR3 0xf80a0000
 224
 225 void __init plat_early_device_setup(void)
 226 {
 227         /* enable CMT clock */
 228         __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
 229
 230         early_platform_add_devices(sh7619_early_devices,
 231                                    ARRAY_SIZE(sh7619_early_devices));
 232 }