spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / sh / kernel / cpu / sh2a / opcode_helper.c
blob9704b7926d8bd30706c19dbb54952d554b708a93
1 /*
2 * arch/sh/kernel/cpu/sh2a/opcode_helper.c
4 * Helper for the SH-2A 32-bit opcodes.
6 * Copyright (C) 2007 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
12 #include <linux/kernel.h>
13 #include <asm/system.h>
16 * Instructions on SH are generally fixed at 16-bits, however, SH-2A
17 * introduces some 32-bit instructions. Since there are no real
18 * constraints on their use (and they can be mixed and matched), we need
19 * to check the instruction encoding to work out if it's a true 32-bit
20 * instruction or not.
22 * Presently, 32-bit opcodes have only slight variations in what the
23 * actual encoding looks like in the first-half of the instruction, which
24 * makes it fairly straightforward to differentiate from the 16-bit ones.
26 * First 16-bits of encoding Used by
28 * 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d,
29 * fmov.s, movu.b, movu.w
31 * 0011nnnn0iii1001 bclr.b, bld.b, bset.b, bst.b, band.b,
32 * bandnot.b, bldnot.b, bor.b, bornot.b,
33 * bxor.b
35 * 0000nnnniiii0000 movi20
36 * 0000nnnniiii0001 movi20s
38 unsigned int instruction_size(unsigned int insn)
40 /* Look for the common cases */
41 switch ((insn & 0xf00f)) {
42 case 0x0000: /* movi20 */
43 case 0x0001: /* movi20s */
44 case 0x3001: /* 32-bit mov/fmov/movu variants */
45 return 4;
48 /* And the special cases.. */
49 switch ((insn & 0xf08f)) {
50 case 0x3009: /* 32-bit b*.b bit operations */
51 return 4;
54 return 2;