spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / sh / kernel / cpu / sh3 / serial-sh770x.c
blob4f7242c676b37fdea21467775f5bfe79518b9efe
1 #include <linux/serial_sci.h>
2 #include <linux/serial_core.h>
3 #include <linux/io.h>
4 #include <cpu/serial.h>
6 #define SCPCR 0xA4000116
7 #define SCPDR 0xA4000136
9 static void sh770x_sci_init_pins(struct uart_port *port, unsigned int cflag)
11 unsigned short data;
13 /* We need to set SCPCR to enable RTS/CTS */
14 data = __raw_readw(SCPCR);
15 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
16 __raw_writew(data & 0x0fcf, SCPCR);
18 if (!(cflag & CRTSCTS)) {
19 /* We need to set SCPCR to enable RTS/CTS */
20 data = __raw_readw(SCPCR);
21 /* Clear out SCP7MD1,0, SCP4MD1,0,
22 Set SCP6MD1,0 = {01} (output) */
23 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
25 data = __raw_readb(SCPDR);
26 /* Set /RTS2 (bit6) = 0 */
27 __raw_writeb(data & 0xbf, SCPDR);
31 struct plat_sci_port_ops sh770x_sci_port_ops = {
32 .init_pins = sh770x_sci_init_pins,