arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17 #include <linux/serial_sci.h>
  18
  19 static struct plat_sci_port scif0_platform_data = {
  20         .mapbase        = 0xffe00000,
  21         .flags          = UPF_BOOT_AUTOCONF,
  22         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  23         .scbrr_algo_id  = SCBRR_ALGO_2,
  24         .type           = PORT_SCIF,
  25         .irqs           = { 40, 40, 40, 40 },
  26         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  27 };
  28
  29 static struct platform_device scif0_device = {
  30         .name           = "sh-sci",
  31         .id             = 0,
  32         .dev            = {
  33                 .platform_data  = &scif0_platform_data,
  34         },
  35 };
  36
  37 static struct plat_sci_port scif1_platform_data = {
  38         .mapbase        = 0xffe08000,
  39         .flags          = UPF_BOOT_AUTOCONF,
  40         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  41         .scbrr_algo_id  = SCBRR_ALGO_2,
  42         .type           = PORT_SCIF,
  43         .irqs           = { 76, 76, 76, 76 },
  44         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  45 };
  46
  47 static struct platform_device scif1_device = {
  48         .name           = "sh-sci",
  49         .id             = 1,
  50         .dev            = {
  51                 .platform_data  = &scif1_platform_data,
  52         },
  53 };
  54
  55 static struct plat_sci_port scif2_platform_data = {
  56         .mapbase        = 0xffe10000,
  57         .flags          = UPF_BOOT_AUTOCONF,
  58         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  59         .scbrr_algo_id  = SCBRR_ALGO_2,
  60         .type           = PORT_SCIF,
  61         .irqs           = { 104, 104, 104, 104 },
  62         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  63 };
  64
  65 static struct platform_device scif2_device = {
  66         .name           = "sh-sci",
  67         .id             = 2,
  68         .dev            = {
  69                 .platform_data  = &scif2_platform_data,
  70         },
  71 };
  72
  73 static struct resource rtc_resources[] = {
  74         [0] = {
  75                 .start  = 0xffe80000,
  76                 .end    = 0xffe80000 + 0x58 - 1,
  77                 .flags  = IORESOURCE_IO,
  78         },
  79         [1] = {
  80                 /* Shared Period/Carry/Alarm IRQ */
  81                 .start  = 20,
  82                 .flags  = IORESOURCE_IRQ,
  83         },
  84 };
  85
  86 static struct platform_device rtc_device = {
  87         .name           = "sh-rtc",
  88         .id             = -1,
  89         .num_resources  = ARRAY_SIZE(rtc_resources),
  90         .resource       = rtc_resources,
  91 };
  92
  93 static struct resource usb_ohci_resources[] = {
  94         [0] = {
  95                 .start  = 0xffec8000,
  96                 .end    = 0xffec80ff,
  97                 .flags  = IORESOURCE_MEM,
  98         },
  99         [1] = {
 100                 .start  = 83,
 101                 .end    = 83,
 102                 .flags  = IORESOURCE_IRQ,
 103         },
 104 };
 105
 106 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 107 static struct platform_device usb_ohci_device = {
 108         .name           = "sh_ohci",
 109         .id             = -1,
 110         .dev = {
 111                 .dma_mask               = &usb_ohci_dma_mask,
 112                 .coherent_dma_mask      = 0xffffffff,
 113         },
 114         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 115         .resource       = usb_ohci_resources,
 116 };
 117
 118 static struct resource usbf_resources[] = {
 119         [0] = {
 120                 .start  = 0xffec0000,
 121                 .end    = 0xffec00ff,
 122                 .flags  = IORESOURCE_MEM,
 123         },
 124         [1] = {
 125                 .start  = 84,
 126                 .end    = 84,
 127                 .flags  = IORESOURCE_IRQ,
 128         },
 129 };
 130
 131 static struct platform_device usbf_device = {
 132         .name           = "sh_udc",
 133         .id             = -1,
 134         .dev = {
 135                 .dma_mask               = NULL,
 136                 .coherent_dma_mask      = 0xffffffff,
 137         },
 138         .num_resources  = ARRAY_SIZE(usbf_resources),
 139         .resource       = usbf_resources,
 140 };
 141
 142 static struct sh_timer_config tmu0_platform_data = {
 143         .channel_offset = 0x04,
 144         .timer_bit = 0,
 145         .clockevent_rating = 200,
 146 };
 147
 148 static struct resource tmu0_resources[] = {
 149         [0] = {
 150                 .start  = 0xffd80008,
 151                 .end    = 0xffd80013,
 152                 .flags  = IORESOURCE_MEM,
 153         },
 154         [1] = {
 155                 .start  = 28,
 156                 .flags  = IORESOURCE_IRQ,
 157         },
 158 };
 159
 160 static struct platform_device tmu0_device = {
 161         .name           = "sh_tmu",
 162         .id             = 0,
 163         .dev = {
 164                 .platform_data  = &tmu0_platform_data,
 165         },
 166         .resource       = tmu0_resources,
 167         .num_resources  = ARRAY_SIZE(tmu0_resources),
 168 };
 169
 170 static struct sh_timer_config tmu1_platform_data = {
 171         .channel_offset = 0x10,
 172         .timer_bit = 1,
 173         .clocksource_rating = 200,
 174 };
 175
 176 static struct resource tmu1_resources[] = {
 177         [0] = {
 178                 .start  = 0xffd80014,
 179                 .end    = 0xffd8001f,
 180                 .flags  = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .start  = 29,
 184                 .flags  = IORESOURCE_IRQ,
 185         },
 186 };
 187
 188 static struct platform_device tmu1_device = {
 189         .name           = "sh_tmu",
 190         .id             = 1,
 191         .dev = {
 192                 .platform_data  = &tmu1_platform_data,
 193         },
 194         .resource       = tmu1_resources,
 195         .num_resources  = ARRAY_SIZE(tmu1_resources),
 196 };
 197
 198 static struct sh_timer_config tmu2_platform_data = {
 199         .channel_offset = 0x1c,
 200         .timer_bit = 2,
 201 };
 202
 203 static struct resource tmu2_resources[] = {
 204         [0] = {
 205                 .start  = 0xffd80020,
 206                 .end    = 0xffd8002f,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         [1] = {
 210                 .start  = 30,
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213 };
 214
 215 static struct platform_device tmu2_device = {
 216         .name           = "sh_tmu",
 217         .id             = 2,
 218         .dev = {
 219                 .platform_data  = &tmu2_platform_data,
 220         },
 221         .resource       = tmu2_resources,
 222         .num_resources  = ARRAY_SIZE(tmu2_resources),
 223 };
 224
 225 static struct sh_timer_config tmu3_platform_data = {
 226         .channel_offset = 0x04,
 227         .timer_bit = 0,
 228 };
 229
 230 static struct resource tmu3_resources[] = {
 231         [0] = {
 232                 .start  = 0xffd88008,
 233                 .end    = 0xffd88013,
 234                 .flags  = IORESOURCE_MEM,
 235         },
 236         [1] = {
 237                 .start  = 96,
 238                 .flags  = IORESOURCE_IRQ,
 239         },
 240 };
 241
 242 static struct platform_device tmu3_device = {
 243         .name           = "sh_tmu",
 244         .id             = 3,
 245         .dev = {
 246                 .platform_data  = &tmu3_platform_data,
 247         },
 248         .resource       = tmu3_resources,
 249         .num_resources  = ARRAY_SIZE(tmu3_resources),
 250 };
 251
 252 static struct sh_timer_config tmu4_platform_data = {
 253         .channel_offset = 0x10,
 254         .timer_bit = 1,
 255 };
 256
 257 static struct resource tmu4_resources[] = {
 258         [0] = {
 259                 .start  = 0xffd88014,
 260                 .end    = 0xffd8801f,
 261                 .flags  = IORESOURCE_MEM,
 262         },
 263         [1] = {
 264                 .start  = 97,
 265                 .flags  = IORESOURCE_IRQ,
 266         },
 267 };
 268
 269 static struct platform_device tmu4_device = {
 270         .name           = "sh_tmu",
 271         .id             = 4,
 272         .dev = {
 273                 .platform_data  = &tmu4_platform_data,
 274         },
 275         .resource       = tmu4_resources,
 276         .num_resources  = ARRAY_SIZE(tmu4_resources),
 277 };
 278
 279 static struct sh_timer_config tmu5_platform_data = {
 280         .channel_offset = 0x1c,
 281         .timer_bit = 2,
 282 };
 283
 284 static struct resource tmu5_resources[] = {
 285         [0] = {
 286                 .start  = 0xffd88020,
 287                 .end    = 0xffd8802b,
 288                 .flags  = IORESOURCE_MEM,
 289         },
 290         [1] = {
 291                 .start  = 98,
 292                 .flags  = IORESOURCE_IRQ,
 293         },
 294 };
 295
 296 static struct platform_device tmu5_device = {
 297         .name           = "sh_tmu",
 298         .id             = 5,
 299         .dev = {
 300                 .platform_data  = &tmu5_platform_data,
 301         },
 302         .resource       = tmu5_resources,
 303         .num_resources  = ARRAY_SIZE(tmu5_resources),
 304 };
 305
 306 static struct platform_device *sh7763_devices[] __initdata = {
 307         &scif0_device,
 308         &scif1_device,
 309         &scif2_device,
 310         &tmu0_device,
 311         &tmu1_device,
 312         &tmu2_device,
 313         &tmu3_device,
 314         &tmu4_device,
 315         &tmu5_device,
 316         &rtc_device,
 317         &usb_ohci_device,
 318         &usbf_device,
 319 };
 320
 321 static int __init sh7763_devices_setup(void)
 322 {
 323         return platform_add_devices(sh7763_devices,
 324                                     ARRAY_SIZE(sh7763_devices));
 325 }
 326 arch_initcall(sh7763_devices_setup);
 327
 328 static struct platform_device *sh7763_early_devices[] __initdata = {
 329         &scif0_device,
 330         &scif1_device,
 331         &scif2_device,
 332         &tmu0_device,
 333         &tmu1_device,
 334         &tmu2_device,
 335         &tmu3_device,
 336         &tmu4_device,
 337         &tmu5_device,
 338 };
 339
 340 void __init plat_early_device_setup(void)
 341 {
 342         early_platform_add_devices(sh7763_early_devices,
 343                                    ARRAY_SIZE(sh7763_early_devices));
 344 }
 345
 346 enum {
 347         UNUSED = 0,
 348
 349         /* interrupt sources */
 350
 351         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 352         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 353         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 354         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 355
 356         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 357         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 358         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 359         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 360         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 361         USBH, USBF, TPU, PCC, MMCIF, SIM,
 362         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 363         SCIF2, GPIO,
 364
 365         /* interrupt groups */
 366
 367         TMU012, TMU345,
 368 };
 369
 370 static struct intc_vect vectors[] __initdata = {
 371         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 372         INTC_VECT(RTC, 0x4c0),
 373         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 374         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 375         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 376         INTC_VECT(LCDC, 0x620),
 377         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 378         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 379         INTC_VECT(DMAC, 0x6c0),
 380         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 381         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 382         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 383         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 384         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 385         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 386         INTC_VECT(HAC, 0x980),
 387         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 388         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 389         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 390         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 391         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 392         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 393         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 394         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 395         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 396         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 397         INTC_VECT(USBF, 0xca0),
 398         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 399         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 400         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 401         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 402         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 403         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 404         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 405         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 406         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 407         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 408         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 409         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 410         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 411 };
 412
 413 static struct intc_group groups[] __initdata = {
 414         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 415         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 416 };
 417
 418 static struct intc_mask_reg mask_registers[] __initdata = {
 419         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 420           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 421             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 422             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 423             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 424         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 425           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 426             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 427             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 428             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 429 };
 430
 431 static struct intc_prio_reg prio_registers[] __initdata = {
 432         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 433                                                  TMU2, TMU2_TICPI } },
 434         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 435         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 436         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 437         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 438                                                  PCISERR, PCIINTA } },
 439         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 440                                                  PCIINTD, PCIC5 } },
 441         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 442         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 443         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 444         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 445         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 446         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 447         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 448         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 449 };
 450
 451 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 452                          mask_registers, prio_registers, NULL);
 453
 454 /* Support for external interrupt pins in IRQ mode */
 455 static struct intc_vect irq_vectors[] __initdata = {
 456         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 457         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 458         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 459         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 460 };
 461
 462 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 463         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 464           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 465 };
 466
 467 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 468         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 469                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 470 };
 471
 472 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 473         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 474                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 475 };
 476
 477 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 478         { 0xffd00024, 0, 32, /* INTREQ */
 479           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 480 };
 481
 482 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 483                              NULL, irq_mask_registers, irq_prio_registers,
 484                              irq_sense_registers, irq_ack_registers);
 485
 486
 487 /* External interrupt pins in IRL mode */
 488 static struct intc_vect irl_vectors[] __initdata = {
 489         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 490         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 491         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 492         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 493         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 494         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 495         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 496         INTC_VECT(IRL_HHHL, 0x3c0),
 497 };
 498
 499 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 500         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 501           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 502             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 503             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 504             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 505 };
 506
 507 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 508         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 509           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 510             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 511             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 512             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 513             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 514 };
 515
 516 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 517                         NULL, irl7654_mask_registers, NULL, NULL);
 518
 519 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 520                         NULL, irl3210_mask_registers, NULL, NULL);
 521
 522 #define INTC_ICR0       0xffd00000
 523 #define INTC_INTMSK0    0xffd00044
 524 #define INTC_INTMSK1    0xffd00048
 525 #define INTC_INTMSK2    0xffd40080
 526 #define INTC_INTMSKCLR1 0xffd00068
 527 #define INTC_INTMSKCLR2 0xffd40084
 528
 529 void __init plat_irq_setup(void)
 530 {
 531         /* disable IRQ7-0 */
 532         __raw_writel(0xff000000, INTC_INTMSK0);
 533
 534         /* disable IRL3-0 + IRL7-4 */
 535         __raw_writel(0xc0000000, INTC_INTMSK1);
 536         __raw_writel(0xfffefffe, INTC_INTMSK2);
 537
 538         register_intc_controller(&intc_desc);
 539 }
 540
 541 void __init plat_irq_setup_pins(int mode)
 542 {
 543         switch (mode) {
 544         case IRQ_MODE_IRQ:
 545                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 546                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 547                 register_intc_controller(&intc_irq_desc);
 548                 break;
 549         case IRQ_MODE_IRL7654:
 550                 /* enable IRL7-4 but don't provide any masking */
 551                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 552                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 553                 break;
 554         case IRQ_MODE_IRL3210:
 555                 /* enable IRL0-3 but don't provide any masking */
 556                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 557                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 558                 break;
 559         case IRQ_MODE_IRL7654_MASK:
 560                 /* enable IRL7-4 and mask using cpu intc controller */
 561                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 562                 register_intc_controller(&intc_irl7654_desc);
 563                 break;
 564         case IRQ_MODE_IRL3210_MASK:
 565                 /* enable IRL0-3 and mask using cpu intc controller */
 566                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 567                 register_intc_controller(&intc_irl3210_desc);
 568                 break;
 569         default:
 570                 BUG();
 571         }
 572 }