spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / sh / mm / cache-shx3.c
blobc0adbee97b5f29a2cdb33f6124c1d62ee821ebec
1 /*
2 * arch/sh/mm/cache-shx3.c - SH-X3 optimized cache ops
4 * Copyright (C) 2010 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/io.h>
13 #include <asm/cache.h>
15 #define CCR_CACHE_SNM 0x40000 /* Hardware-assisted synonym avoidance */
16 #define CCR_CACHE_IBE 0x1000000 /* ICBI broadcast */
18 void __init shx3_cache_init(void)
20 unsigned int ccr;
22 ccr = __raw_readl(CCR);
25 * If we've got cache aliases, resolve them in hardware.
27 if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) {
28 ccr |= CCR_CACHE_SNM;
30 boot_cpu_data.icache.n_aliases = 0;
31 boot_cpu_data.dcache.n_aliases = 0;
33 pr_info("Enabling hardware synonym avoidance\n");
36 #ifdef CONFIG_SMP
38 * Broadcast I-cache block invalidations by default.
40 ccr |= CCR_CACHE_IBE;
41 #endif
43 writel_uncached(ccr, CCR);