spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / arch / unicore32 / mm / flush.c
blob93478cc8b26dc430beba5b3a60387a5ad60f87c5
1 /*
2 * linux/arch/unicore32/mm/flush.c
4 * Code specific to PKUnity SoC and UniCore ISA
6 * Copyright (C) 2001-2010 GUAN Xue-tao
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/mm.h>
14 #include <linux/pagemap.h>
16 #include <asm/cacheflush.h>
17 #include <asm/system.h>
18 #include <asm/tlbflush.h>
20 void flush_cache_mm(struct mm_struct *mm)
24 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
25 unsigned long end)
27 if (vma->vm_flags & VM_EXEC)
28 __flush_icache_all();
31 void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr,
32 unsigned long pfn)
36 static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
37 unsigned long uaddr, void *kaddr, unsigned long len)
39 /* VIPT non-aliasing D-cache */
40 if (vma->vm_flags & VM_EXEC) {
41 unsigned long addr = (unsigned long)kaddr;
43 __cpuc_coherent_kern_range(addr, addr + len);
48 * Copy user data from/to a page which is mapped into a different
49 * processes address space. Really, we want to allow our "user
50 * space" model to handle this.
52 * Note that this code needs to run on the current CPU.
54 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
55 unsigned long uaddr, void *dst, const void *src,
56 unsigned long len)
58 memcpy(dst, src, len);
59 flush_ptrace_access(vma, page, uaddr, dst, len);
62 void __flush_dcache_page(struct address_space *mapping, struct page *page)
65 * Writeback any data associated with the kernel mapping of this
66 * page. This ensures that data in the physical page is mutually
67 * coherent with the kernels mapping.
69 __cpuc_flush_kern_dcache_area(page_address(page), PAGE_SIZE);
73 * Ensure cache coherency between kernel mapping and userspace mapping
74 * of this page.
76 void flush_dcache_page(struct page *page)
78 struct address_space *mapping;
81 * The zero page is never written to, so never has any dirty
82 * cache lines, and therefore never needs to be flushed.
84 if (page == ZERO_PAGE(0))
85 return;
87 mapping = page_mapping(page);
89 if (mapping && !mapping_mapped(mapping))
90 clear_bit(PG_dcache_clean, &page->flags);
91 else {
92 __flush_dcache_page(mapping, page);
93 if (mapping)
94 __flush_icache_all();
95 set_bit(PG_dcache_clean, &page->flags);
98 EXPORT_SYMBOL(flush_dcache_page);