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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / dma / mxs-dma.c
blobb06cd4ca626fb4fd93d5ab3b7fedddbfd6ea6c25
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Refer to drivers/dma/imx-sdma.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/mm.h>
14 #include <linux/interrupt.h>
15 #include <linux/clk.h>
16 #include <linux/wait.h>
17 #include <linux/sched.h>
18 #include <linux/semaphore.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25
26 #include <asm/irq.h>
27 #include <mach/mxs.h>
28 #include <mach/dma.h>
29 #include <mach/common.h>
30
31 /*
32 * NOTE: The term "PIO" throughout the mxs-dma implementation means
33 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
34 * dma can program the controller registers of peripheral devices.
35 */
36
37 #define MXS_DMA_APBH 0
38 #define MXS_DMA_APBX 1
39 #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
40
41 #define APBH_VERSION_LATEST 3
42 #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
43
44 #define HW_APBHX_CTRL0 0x000
45 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
46 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
47 #define BP_APBH_CTRL0_RESET_CHANNEL 16
48 #define HW_APBHX_CTRL1 0x010
49 #define HW_APBHX_CTRL2 0x020
50 #define HW_APBHX_CHANNEL_CTRL 0x030
51 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
52 #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
53 #define HW_APBX_VERSION 0x800
54 #define BP_APBHX_VERSION_MAJOR 24
55 #define HW_APBHX_CHn_NXTCMDAR(n) \
56 (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
57 #define HW_APBHX_CHn_SEMA(n) \
58 (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
59
60 /*
61 * ccw bits definitions
62 *
63 * COMMAND: 0..1 (2)
64 * CHAIN: 2 (1)
65 * IRQ: 3 (1)
66 * NAND_LOCK: 4 (1) - not implemented
67 * NAND_WAIT4READY: 5 (1) - not implemented
68 * DEC_SEM: 6 (1)
69 * WAIT4END: 7 (1)
70 * HALT_ON_TERMINATE: 8 (1)
71 * TERMINATE_FLUSH: 9 (1)
72 * RESERVED: 10..11 (2)
73 * PIO_NUM: 12..15 (4)
74 */
75 #define BP_CCW_COMMAND 0
76 #define BM_CCW_COMMAND (3 << 0)
77 #define CCW_CHAIN (1 << 2)
78 #define CCW_IRQ (1 << 3)
79 #define CCW_DEC_SEM (1 << 6)
80 #define CCW_WAIT4END (1 << 7)
81 #define CCW_HALT_ON_TERM (1 << 8)
82 #define CCW_TERM_FLUSH (1 << 9)
83 #define BP_CCW_PIO_NUM 12
84 #define BM_CCW_PIO_NUM (0xf << 12)
85
86 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
87
88 #define MXS_DMA_CMD_NO_XFER 0
89 #define MXS_DMA_CMD_WRITE 1
90 #define MXS_DMA_CMD_READ 2
91 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
92
93 struct mxs_dma_ccw {
94 u32 next;
95 u16 bits;
96 u16 xfer_bytes;
97 #define MAX_XFER_BYTES 0xff00
98 u32 bufaddr;
99 #define MXS_PIO_WORDS 16
100 u32 pio_words[MXS_PIO_WORDS];
101 };
102
103 #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
104
105 struct mxs_dma_chan {
106 struct mxs_dma_engine *mxs_dma;
107 struct dma_chan chan;
108 struct dma_async_tx_descriptor desc;
109 struct tasklet_struct tasklet;
110 int chan_irq;
111 struct mxs_dma_ccw *ccw;
112 dma_addr_t ccw_phys;
113 int desc_count;
114 dma_cookie_t last_completed;
115 enum dma_status status;
116 unsigned int flags;
117 #define MXS_DMA_SG_LOOP (1 << 0)
118 };
119
120 #define MXS_DMA_CHANNELS 16
121 #define MXS_DMA_CHANNELS_MASK 0xffff
122
123 struct mxs_dma_engine {
124 int dev_id;
125 unsigned int version;
126 void __iomem *base;
127 struct clk *clk;
128 struct dma_device dma_device;
129 struct device_dma_parameters dma_parms;
130 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
131 };
132
133 static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
134 {
135 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
136 int chan_id = mxs_chan->chan.chan_id;
137
138 if (dma_is_apbh() && apbh_is_old())
139 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
140 mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
141 else
142 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
143 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
144 }
145
146 static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
147 {
148 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
149 int chan_id = mxs_chan->chan.chan_id;
150
151 /* set cmd_addr up */
152 writel(mxs_chan->ccw_phys,
153 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
154
155 /* write 1 to SEMA to kick off the channel */
156 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
157 }
158
159 static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
160 {
161 mxs_chan->status = DMA_SUCCESS;
162 }
163
164 static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
165 {
166 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
167 int chan_id = mxs_chan->chan.chan_id;
168
169 /* freeze the channel */
170 if (dma_is_apbh() && apbh_is_old())
171 writel(1 << chan_id,
172 mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
173 else
174 writel(1 << chan_id,
175 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
176
177 mxs_chan->status = DMA_PAUSED;
178 }
179
180 static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
181 {
182 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
183 int chan_id = mxs_chan->chan.chan_id;
184
185 /* unfreeze the channel */
186 if (dma_is_apbh() && apbh_is_old())
187 writel(1 << chan_id,
188 mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
189 else
190 writel(1 << chan_id,
191 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
192
193 mxs_chan->status = DMA_IN_PROGRESS;
194 }
195
196 static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
197 {
198 dma_cookie_t cookie = mxs_chan->chan.cookie;
199
200 if (++cookie < 0)
201 cookie = 1;
202
203 mxs_chan->chan.cookie = cookie;
204 mxs_chan->desc.cookie = cookie;
205
206 return cookie;
207 }
208
209 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
210 {
211 return container_of(chan, struct mxs_dma_chan, chan);
212 }
213
214 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
215 {
216 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
217
218 mxs_dma_enable_chan(mxs_chan);
219
220 return mxs_dma_assign_cookie(mxs_chan);
221 }
222
223 static void mxs_dma_tasklet(unsigned long data)
224 {
225 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
226
227 if (mxs_chan->desc.callback)
228 mxs_chan->desc.callback(mxs_chan->desc.callback_param);
229 }
230
231 static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
232 {
233 struct mxs_dma_engine *mxs_dma = dev_id;
234 u32 stat1, stat2;
235
236 /* completion status */
237 stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
238 stat1 &= MXS_DMA_CHANNELS_MASK;
239 writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
240
241 /* error status */
242 stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
243 writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
244
245 /*
246 * When both completion and error of termination bits set at the
247 * same time, we do not take it as an error. IOW, it only becomes
248 * an error we need to handle here in case of either it's (1) a bus
249 * error or (2) a termination error with no completion.
250 */
251 stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
252 (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
253
254 /* combine error and completion status for checking */
255 stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
256 while (stat1) {
257 int channel = fls(stat1) - 1;
258 struct mxs_dma_chan *mxs_chan =
259 &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
260
261 if (channel >= MXS_DMA_CHANNELS) {
262 dev_dbg(mxs_dma->dma_device.dev,
263 "%s: error in channel %d\n", __func__,
264 channel - MXS_DMA_CHANNELS);
265 mxs_chan->status = DMA_ERROR;
266 mxs_dma_reset_chan(mxs_chan);
267 } else {
268 if (mxs_chan->flags & MXS_DMA_SG_LOOP)
269 mxs_chan->status = DMA_IN_PROGRESS;
270 else
271 mxs_chan->status = DMA_SUCCESS;
272 }
273
274 stat1 &= ~(1 << channel);
275
276 if (mxs_chan->status == DMA_SUCCESS)
277 mxs_chan->last_completed = mxs_chan->desc.cookie;
278
279 /* schedule tasklet on this channel */
280 tasklet_schedule(&mxs_chan->tasklet);
281 }
282
283 return IRQ_HANDLED;
284 }
285
286 static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
287 {
288 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
289 struct mxs_dma_data *data = chan->private;
290 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
291 int ret;
292
293 if (!data)
294 return -EINVAL;
295
296 mxs_chan->chan_irq = data->chan_irq;
297
298 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
299 &mxs_chan->ccw_phys, GFP_KERNEL);
300 if (!mxs_chan->ccw) {
301 ret = -ENOMEM;
302 goto err_alloc;
303 }
304
305 memset(mxs_chan->ccw, 0, PAGE_SIZE);
306
307 if (mxs_chan->chan_irq != NO_IRQ) {
308 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
309 0, "mxs-dma", mxs_dma);
310 if (ret)
311 goto err_irq;
312 }
313
314 ret = clk_prepare_enable(mxs_dma->clk);
315 if (ret)
316 goto err_clk;
317
318 mxs_dma_reset_chan(mxs_chan);
319
320 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
321 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
322
323 /* the descriptor is ready */
324 async_tx_ack(&mxs_chan->desc);
325
326 return 0;
327
328 err_clk:
329 free_irq(mxs_chan->chan_irq, mxs_dma);
330 err_irq:
331 dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
332 mxs_chan->ccw, mxs_chan->ccw_phys);
333 err_alloc:
334 return ret;
335 }
336
337 static void mxs_dma_free_chan_resources(struct dma_chan *chan)
338 {
339 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
340 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
341
342 mxs_dma_disable_chan(mxs_chan);
343
344 free_irq(mxs_chan->chan_irq, mxs_dma);
345
346 dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
347 mxs_chan->ccw, mxs_chan->ccw_phys);
348
349 clk_disable_unprepare(mxs_dma->clk);
350 }
351
352 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
353 struct dma_chan *chan, struct scatterlist *sgl,
354 unsigned int sg_len, enum dma_transfer_direction direction,
355 unsigned long append)
356 {
357 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
358 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
359 struct mxs_dma_ccw *ccw;
360 struct scatterlist *sg;
361 int i, j;
362 u32 *pio;
363 int idx = append ? mxs_chan->desc_count : 0;
364
365 if (mxs_chan->status == DMA_IN_PROGRESS && !append)
366 return NULL;
367
368 if (sg_len + (append ? idx : 0) > NUM_CCW) {
369 dev_err(mxs_dma->dma_device.dev,
370 "maximum number of sg exceeded: %d > %d\n",
371 sg_len, NUM_CCW);
372 goto err_out;
373 }
374
375 mxs_chan->status = DMA_IN_PROGRESS;
376 mxs_chan->flags = 0;
377
378 /*
379 * If the sg is prepared with append flag set, the sg
380 * will be appended to the last prepared sg.
381 */
382 if (append) {
383 BUG_ON(idx < 1);
384 ccw = &mxs_chan->ccw[idx - 1];
385 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
386 ccw->bits |= CCW_CHAIN;
387 ccw->bits &= ~CCW_IRQ;
388 ccw->bits &= ~CCW_DEC_SEM;
389 ccw->bits &= ~CCW_WAIT4END;
390 } else {
391 idx = 0;
392 }
393
394 if (direction == DMA_TRANS_NONE) {
395 ccw = &mxs_chan->ccw[idx++];
396 pio = (u32 *) sgl;
397
398 for (j = 0; j < sg_len;)
399 ccw->pio_words[j++] = *pio++;
400
401 ccw->bits = 0;
402 ccw->bits |= CCW_IRQ;
403 ccw->bits |= CCW_DEC_SEM;
404 ccw->bits |= CCW_WAIT4END;
405 ccw->bits |= CCW_HALT_ON_TERM;
406 ccw->bits |= CCW_TERM_FLUSH;
407 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
408 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
409 } else {
410 for_each_sg(sgl, sg, sg_len, i) {
411 if (sg->length > MAX_XFER_BYTES) {
412 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
413 sg->length, MAX_XFER_BYTES);
414 goto err_out;
415 }
416
417 ccw = &mxs_chan->ccw[idx++];
418
419 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
420 ccw->bufaddr = sg->dma_address;
421 ccw->xfer_bytes = sg->length;
422
423 ccw->bits = 0;
424 ccw->bits |= CCW_CHAIN;
425 ccw->bits |= CCW_HALT_ON_TERM;
426 ccw->bits |= CCW_TERM_FLUSH;
427 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
428 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
429 COMMAND);
430
431 if (i + 1 == sg_len) {
432 ccw->bits &= ~CCW_CHAIN;
433 ccw->bits |= CCW_IRQ;
434 ccw->bits |= CCW_DEC_SEM;
435 ccw->bits |= CCW_WAIT4END;
436 }
437 }
438 }
439 mxs_chan->desc_count = idx;
440
441 return &mxs_chan->desc;
442
443 err_out:
444 mxs_chan->status = DMA_ERROR;
445 return NULL;
446 }
447
448 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
449 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
450 size_t period_len, enum dma_transfer_direction direction)
451 {
452 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
453 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
454 int num_periods = buf_len / period_len;
455 int i = 0, buf = 0;
456
457 if (mxs_chan->status == DMA_IN_PROGRESS)
458 return NULL;
459
460 mxs_chan->status = DMA_IN_PROGRESS;
461 mxs_chan->flags |= MXS_DMA_SG_LOOP;
462
463 if (num_periods > NUM_CCW) {
464 dev_err(mxs_dma->dma_device.dev,
465 "maximum number of sg exceeded: %d > %d\n",
466 num_periods, NUM_CCW);
467 goto err_out;
468 }
469
470 if (period_len > MAX_XFER_BYTES) {
471 dev_err(mxs_dma->dma_device.dev,
472 "maximum period size exceeded: %d > %d\n",
473 period_len, MAX_XFER_BYTES);
474 goto err_out;
475 }
476
477 while (buf < buf_len) {
478 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
479
480 if (i + 1 == num_periods)
481 ccw->next = mxs_chan->ccw_phys;
482 else
483 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
484
485 ccw->bufaddr = dma_addr;
486 ccw->xfer_bytes = period_len;
487
488 ccw->bits = 0;
489 ccw->bits |= CCW_CHAIN;
490 ccw->bits |= CCW_IRQ;
491 ccw->bits |= CCW_HALT_ON_TERM;
492 ccw->bits |= CCW_TERM_FLUSH;
493 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
494 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
495
496 dma_addr += period_len;
497 buf += period_len;
498
499 i++;
500 }
501 mxs_chan->desc_count = i;
502
503 return &mxs_chan->desc;
504
505 err_out:
506 mxs_chan->status = DMA_ERROR;
507 return NULL;
508 }
509
510 static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
511 unsigned long arg)
512 {
513 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
514 int ret = 0;
515
516 switch (cmd) {
517 case DMA_TERMINATE_ALL:
518 mxs_dma_reset_chan(mxs_chan);
519 mxs_dma_disable_chan(mxs_chan);
520 break;
521 case DMA_PAUSE:
522 mxs_dma_pause_chan(mxs_chan);
523 break;
524 case DMA_RESUME:
525 mxs_dma_resume_chan(mxs_chan);
526 break;
527 default:
528 ret = -ENOSYS;
529 }
530
531 return ret;
532 }
533
534 static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
535 dma_cookie_t cookie, struct dma_tx_state *txstate)
536 {
537 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
538 dma_cookie_t last_used;
539
540 last_used = chan->cookie;
541 dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);
542
543 return mxs_chan->status;
544 }
545
546 static void mxs_dma_issue_pending(struct dma_chan *chan)
547 {
548 /*
549 * Nothing to do. We only have a single descriptor.
550 */
551 }
552
553 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
554 {
555 int ret;
556
557 ret = clk_prepare_enable(mxs_dma->clk);
558 if (ret)
559 return ret;
560
561 ret = mxs_reset_block(mxs_dma->base);
562 if (ret)
563 goto err_out;
564
565 /* only major version matters */
566 mxs_dma->version = readl(mxs_dma->base +
567 ((mxs_dma->dev_id == MXS_DMA_APBX) ?
568 HW_APBX_VERSION : HW_APBH_VERSION)) >>
569 BP_APBHX_VERSION_MAJOR;
570
571 /* enable apbh burst */
572 if (dma_is_apbh()) {
573 writel(BM_APBH_CTRL0_APB_BURST_EN,
574 mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
575 writel(BM_APBH_CTRL0_APB_BURST8_EN,
576 mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
577 }
578
579 /* enable irq for all the channels */
580 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
581 mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
582
583 err_out:
584 clk_disable_unprepare(mxs_dma->clk);
585 return ret;
586 }
587
588 static int __init mxs_dma_probe(struct platform_device *pdev)
589 {
590 const struct platform_device_id *id_entry =
591 platform_get_device_id(pdev);
592 struct mxs_dma_engine *mxs_dma;
593 struct resource *iores;
594 int ret, i;
595
596 mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
597 if (!mxs_dma)
598 return -ENOMEM;
599
600 mxs_dma->dev_id = id_entry->driver_data;
601
602 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
603
604 if (!request_mem_region(iores->start, resource_size(iores),
605 pdev->name)) {
606 ret = -EBUSY;
607 goto err_request_region;
608 }
609
610 mxs_dma->base = ioremap(iores->start, resource_size(iores));
611 if (!mxs_dma->base) {
612 ret = -ENOMEM;
613 goto err_ioremap;
614 }
615
616 mxs_dma->clk = clk_get(&pdev->dev, NULL);
617 if (IS_ERR(mxs_dma->clk)) {
618 ret = PTR_ERR(mxs_dma->clk);
619 goto err_clk;
620 }
621
622 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
623 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
624
625 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
626
627 /* Initialize channel parameters */
628 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
629 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
630
631 mxs_chan->mxs_dma = mxs_dma;
632 mxs_chan->chan.device = &mxs_dma->dma_device;
633
634 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
635 (unsigned long) mxs_chan);
636
637
638 /* Add the channel to mxs_chan list */
639 list_add_tail(&mxs_chan->chan.device_node,
640 &mxs_dma->dma_device.channels);
641 }
642
643 ret = mxs_dma_init(mxs_dma);
644 if (ret)
645 goto err_init;
646
647 mxs_dma->dma_device.dev = &pdev->dev;
648
649 /* mxs_dma gets 65535 bytes maximum sg size */
650 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
651 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
652
653 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
654 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
655 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
656 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
657 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
658 mxs_dma->dma_device.device_control = mxs_dma_control;
659 mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
660
661 ret = dma_async_device_register(&mxs_dma->dma_device);
662 if (ret) {
663 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
664 goto err_init;
665 }
666
667 dev_info(mxs_dma->dma_device.dev, "initialized\n");
668
669 return 0;
670
671 err_init:
672 clk_put(mxs_dma->clk);
673 err_clk:
674 iounmap(mxs_dma->base);
675 err_ioremap:
676 release_mem_region(iores->start, resource_size(iores));
677 err_request_region:
678 kfree(mxs_dma);
679 return ret;
680 }
681
682 static struct platform_device_id mxs_dma_type[] = {
683 {
684 .name = "mxs-dma-apbh",
685 .driver_data = MXS_DMA_APBH,
686 }, {
687 .name = "mxs-dma-apbx",
688 .driver_data = MXS_DMA_APBX,
689 }, {
690 /* end of list */
691 }
692 };
693
694 static struct platform_driver mxs_dma_driver = {
695 .driver = {
696 .name = "mxs-dma",
697 },
698 .id_table = mxs_dma_type,
699 };
700
701 static int __init mxs_dma_module_init(void)
702 {
703 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
704 }
705 subsys_initcall(mxs_dma_module_init);