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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / i2c / busses / i2c-eg20t.c
blob84f98188d817285452b842f9c82577ef6a237c33
1 /*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/i2c.h>
24 #include <linux/fs.h>
25 #include <linux/io.h>
26 #include <linux/types.h>
27 #include <linux/interrupt.h>
28 #include <linux/jiffies.h>
29 #include <linux/pci.h>
30 #include <linux/mutex.h>
31 #include <linux/ktime.h>
32 #include <linux/slab.h>
33
34 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
35 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
36 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
37 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
38 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
39
40 #define PCH_I2CSADR 0x00 /* I2C slave address register */
41 #define PCH_I2CCTL 0x04 /* I2C control register */
42 #define PCH_I2CSR 0x08 /* I2C status register */
43 #define PCH_I2CDR 0x0C /* I2C data register */
44 #define PCH_I2CMON 0x10 /* I2C bus monitor register */
45 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
46 #define PCH_I2CMOD 0x18 /* I2C mode register */
47 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
48 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
49 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
50 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
51 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
52 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
53 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
54 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
55 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
56 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
57 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
58 #define PCH_I2CTMR 0x48 /* I2C timer register */
59 #define PCH_I2CSRST 0xFC /* I2C reset register */
60 #define PCH_I2CNF 0xF8 /* I2C noise filter register */
61
62 #define BUS_IDLE_TIMEOUT 20
63 #define PCH_I2CCTL_I2CMEN 0x0080
64 #define TEN_BIT_ADDR_DEFAULT 0xF000
65 #define TEN_BIT_ADDR_MASK 0xF0
66 #define PCH_START 0x0020
67 #define PCH_RESTART 0x0004
68 #define PCH_ESR_START 0x0001
69 #define PCH_BUFF_START 0x1
70 #define PCH_REPSTART 0x0004
71 #define PCH_ACK 0x0008
72 #define PCH_GETACK 0x0001
73 #define CLR_REG 0x0
74 #define I2C_RD 0x1
75 #define I2CMCF_BIT 0x0080
76 #define I2CMIF_BIT 0x0002
77 #define I2CMAL_BIT 0x0010
78 #define I2CBMFI_BIT 0x0001
79 #define I2CBMAL_BIT 0x0002
80 #define I2CBMNA_BIT 0x0004
81 #define I2CBMTO_BIT 0x0008
82 #define I2CBMIS_BIT 0x0010
83 #define I2CESRFI_BIT 0X0001
84 #define I2CESRTO_BIT 0x0002
85 #define I2CESRFIIE_BIT 0x1
86 #define I2CESRTOIE_BIT 0x2
87 #define I2CBMDZ_BIT 0x0040
88 #define I2CBMAG_BIT 0x0020
89 #define I2CMBB_BIT 0x0020
90 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
91 I2CBMTO_BIT | I2CBMIS_BIT)
92 #define I2C_ADDR_MSK 0xFF
93 #define I2C_MSB_2B_MSK 0x300
94 #define FAST_MODE_CLK 400
95 #define FAST_MODE_EN 0x0001
96 #define SUB_ADDR_LEN_MAX 4
97 #define BUF_LEN_MAX 32
98 #define PCH_BUFFER_MODE 0x1
99 #define EEPROM_SW_RST_MODE 0x0002
100 #define NORMAL_INTR_ENBL 0x0300
101 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
102 #define EEPROM_RST_INTR_DISBL 0x0
103 #define BUFFER_MODE_INTR_ENBL 0x001F
104 #define BUFFER_MODE_INTR_DISBL 0x0
105 #define NORMAL_MODE 0x0
106 #define BUFFER_MODE 0x1
107 #define EEPROM_SR_MODE 0x2
108 #define I2C_TX_MODE 0x0010
109 #define PCH_BUF_TX 0xFFF7
110 #define PCH_BUF_RD 0x0008
111 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
112 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
113 #define I2CMAL_EVENT 0x0001
114 #define I2CMCF_EVENT 0x0002
115 #define I2CBMFI_EVENT 0x0004
116 #define I2CBMAL_EVENT 0x0008
117 #define I2CBMNA_EVENT 0x0010
118 #define I2CBMTO_EVENT 0x0020
119 #define I2CBMIS_EVENT 0x0040
120 #define I2CESRFI_EVENT 0x0080
121 #define I2CESRTO_EVENT 0x0100
122 #define PCI_DEVICE_ID_PCH_I2C 0x8817
123
124 #define pch_dbg(adap, fmt, arg...) \
125 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
126
127 #define pch_err(adap, fmt, arg...) \
128 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
129
130 #define pch_pci_err(pdev, fmt, arg...) \
131 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
132
133 #define pch_pci_dbg(pdev, fmt, arg...) \
134 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
135
136 /*
137 Set the number of I2C instance max
138 Intel EG20T PCH : 1ch
139 LAPIS Semiconductor ML7213 IOH : 2ch
140 LAPIS Semiconductor ML7831 IOH : 1ch
141 */
142 #define PCH_I2C_MAX_DEV 2
143
144 /**
145 * struct i2c_algo_pch_data - for I2C driver functionalities
146 * @pch_adapter: stores the reference to i2c_adapter structure
147 * @p_adapter_info: stores the reference to adapter_info structure
148 * @pch_base_address: specifies the remapped base address
149 * @pch_buff_mode_en: specifies if buffer mode is enabled
150 * @pch_event_flag: specifies occurrence of interrupt events
151 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
152 */
153 struct i2c_algo_pch_data {
154 struct i2c_adapter pch_adapter;
155 struct adapter_info *p_adapter_info;
156 void __iomem *pch_base_address;
157 int pch_buff_mode_en;
158 u32 pch_event_flag;
159 bool pch_i2c_xfer_in_progress;
160 };
161
162 /**
163 * struct adapter_info - This structure holds the adapter information for the
164 PCH i2c controller
165 * @pch_data: stores a list of i2c_algo_pch_data
166 * @pch_i2c_suspended: specifies whether the system is suspended or not
167 * perhaps with more lines and words.
168 * @ch_num: specifies the number of i2c instance
169 *
170 * pch_data has as many elements as maximum I2C channels
171 */
172 struct adapter_info {
173 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
174 bool pch_i2c_suspended;
175 int ch_num;
176 };
177
178
179 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
180 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
181 static wait_queue_head_t pch_event;
182 static DEFINE_MUTEX(pch_mutex);
183
184 /* Definition for ML7213 by LAPIS Semiconductor */
185 #define PCI_VENDOR_ID_ROHM 0x10DB
186 #define PCI_DEVICE_ID_ML7213_I2C 0x802D
187 #define PCI_DEVICE_ID_ML7223_I2C 0x8010
188 #define PCI_DEVICE_ID_ML7831_I2C 0x8817
189
190 static DEFINE_PCI_DEVICE_TABLE(pch_pcidev_id) = {
191 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
192 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
193 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
194 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
195 {0,}
196 };
197
198 static irqreturn_t pch_i2c_handler(int irq, void *pData);
199
200 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
201 {
202 u32 val;
203 val = ioread32(addr + offset);
204 val |= bitmask;
205 iowrite32(val, addr + offset);
206 }
207
208 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
209 {
210 u32 val;
211 val = ioread32(addr + offset);
212 val &= (~bitmask);
213 iowrite32(val, addr + offset);
214 }
215
216 /**
217 * pch_i2c_init() - hardware initialization of I2C module
218 * @adap: Pointer to struct i2c_algo_pch_data.
219 */
220 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
221 {
222 void __iomem *p = adap->pch_base_address;
223 u32 pch_i2cbc;
224 u32 pch_i2ctmr;
225 u32 reg_value;
226
227 /* reset I2C controller */
228 iowrite32(0x01, p + PCH_I2CSRST);
229 msleep(20);
230 iowrite32(0x0, p + PCH_I2CSRST);
231
232 /* Initialize I2C registers */
233 iowrite32(0x21, p + PCH_I2CNF);
234
235 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
236
237 if (pch_i2c_speed != 400)
238 pch_i2c_speed = 100;
239
240 reg_value = PCH_I2CCTL_I2CMEN;
241 if (pch_i2c_speed == FAST_MODE_CLK) {
242 reg_value |= FAST_MODE_EN;
243 pch_dbg(adap, "Fast mode enabled\n");
244 }
245
246 if (pch_clk > PCH_MAX_CLK)
247 pch_clk = 62500;
248
249 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
250 /* Set transfer speed in I2CBC */
251 iowrite32(pch_i2cbc, p + PCH_I2CBC);
252
253 pch_i2ctmr = (pch_clk) / 8;
254 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
255
256 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
257 iowrite32(reg_value, p + PCH_I2CCTL);
258
259 pch_dbg(adap,
260 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
261 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
262
263 init_waitqueue_head(&pch_event);
264 }
265
266 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
267 {
268 return cmp1.tv64 < cmp2.tv64;
269 }
270
271 /**
272 * pch_i2c_wait_for_bus_idle() - check the status of bus.
273 * @adap: Pointer to struct i2c_algo_pch_data.
274 * @timeout: waiting time counter (us).
275 */
276 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
277 s32 timeout)
278 {
279 void __iomem *p = adap->pch_base_address;
280 ktime_t ns_val;
281
282 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
283 return 0;
284
285 /* MAX timeout value is timeout*1000*1000nsec */
286 ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
287 do {
288 msleep(20);
289 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
290 return 0;
291 } while (ktime_lt(ktime_get(), ns_val));
292
293 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
294 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
295 pch_i2c_init(adap);
296
297 return -ETIME;
298 }
299
300 /**
301 * pch_i2c_start() - Generate I2C start condition in normal mode.
302 * @adap: Pointer to struct i2c_algo_pch_data.
303 *
304 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
305 */
306 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
307 {
308 void __iomem *p = adap->pch_base_address;
309 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
310 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
311 }
312
313 /**
314 * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
315 * @adap: Pointer to struct i2c_algo_pch_data.
316 */
317 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
318 {
319 long ret;
320 ret = wait_event_timeout(pch_event,
321 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
322
323 if (ret == 0) {
324 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
325 adap->pch_event_flag = 0;
326 return -ETIMEDOUT;
327 }
328
329 if (adap->pch_event_flag & I2C_ERROR_MASK) {
330 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
331 adap->pch_event_flag = 0;
332 return -EIO;
333 }
334
335 adap->pch_event_flag = 0;
336
337 return 0;
338 }
339
340 /**
341 * pch_i2c_getack() - to confirm ACK/NACK
342 * @adap: Pointer to struct i2c_algo_pch_data.
343 */
344 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
345 {
346 u32 reg_val;
347 void __iomem *p = adap->pch_base_address;
348 reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
349
350 if (reg_val != 0) {
351 pch_err(adap, "return%d\n", -EPROTO);
352 return -EPROTO;
353 }
354
355 return 0;
356 }
357
358 /**
359 * pch_i2c_stop() - generate stop condition in normal mode.
360 * @adap: Pointer to struct i2c_algo_pch_data.
361 */
362 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
363 {
364 void __iomem *p = adap->pch_base_address;
365 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
366 /* clear the start bit */
367 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
368 }
369
370 /**
371 * pch_i2c_repstart() - generate repeated start condition in normal mode
372 * @adap: Pointer to struct i2c_algo_pch_data.
373 */
374 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
375 {
376 void __iomem *p = adap->pch_base_address;
377 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
378 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
379 }
380
381 /**
382 * pch_i2c_writebytes() - write data to I2C bus in normal mode
383 * @i2c_adap: Pointer to the struct i2c_adapter.
384 * @last: specifies whether last message or not.
385 * In the case of compound mode it will be 1 for last message,
386 * otherwise 0.
387 * @first: specifies whether first message or not.
388 * 1 for first message otherwise 0.
389 */
390 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
391 struct i2c_msg *msgs, u32 last, u32 first)
392 {
393 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
394 u8 *buf;
395 u32 length;
396 u32 addr;
397 u32 addr_2_msb;
398 u32 addr_8_lsb;
399 s32 wrcount;
400 s32 rtn;
401 void __iomem *p = adap->pch_base_address;
402
403 length = msgs->len;
404 buf = msgs->buf;
405 addr = msgs->addr;
406
407 /* enable master tx */
408 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
409
410 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
411 length);
412
413 if (first) {
414 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
415 return -ETIME;
416 }
417
418 if (msgs->flags & I2C_M_TEN) {
419 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
420 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
421 if (first)
422 pch_i2c_start(adap);
423
424 rtn = pch_i2c_wait_for_xfer_complete(adap);
425 if (rtn == 0) {
426 if (pch_i2c_getack(adap)) {
427 pch_dbg(adap, "Receive NACK for slave address"
428 "setting\n");
429 return -EIO;
430 }
431 addr_8_lsb = (addr & I2C_ADDR_MSK);
432 iowrite32(addr_8_lsb, p + PCH_I2CDR);
433 } else if (rtn == -EIO) { /* Arbitration Lost */
434 pch_err(adap, "Lost Arbitration\n");
435 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
436 I2CMAL_BIT);
437 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
438 I2CMIF_BIT);
439 pch_i2c_init(adap);
440 return -EAGAIN;
441 } else { /* wait-event timeout */
442 pch_i2c_stop(adap);
443 return -ETIME;
444 }
445 } else {
446 /* set 7 bit slave address and R/W bit as 0 */
447 iowrite32(addr << 1, p + PCH_I2CDR);
448 if (first)
449 pch_i2c_start(adap);
450 }
451
452 rtn = pch_i2c_wait_for_xfer_complete(adap);
453 if (rtn == 0) {
454 if (pch_i2c_getack(adap)) {
455 pch_dbg(adap, "Receive NACK for slave address"
456 "setting\n");
457 return -EIO;
458 }
459 } else if (rtn == -EIO) { /* Arbitration Lost */
460 pch_err(adap, "Lost Arbitration\n");
461 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
462 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
463 pch_i2c_init(adap);
464 return -EAGAIN;
465 } else { /* wait-event timeout */
466 pch_i2c_stop(adap);
467 return -ETIME;
468 }
469
470 for (wrcount = 0; wrcount < length; ++wrcount) {
471 /* write buffer value to I2C data register */
472 iowrite32(buf[wrcount], p + PCH_I2CDR);
473 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
474
475 rtn = pch_i2c_wait_for_xfer_complete(adap);
476 if (rtn == 0) {
477 if (pch_i2c_getack(adap)) {
478 pch_dbg(adap, "Receive NACK for slave address"
479 "setting\n");
480 return -EIO;
481 }
482 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
483 I2CMCF_BIT);
484 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
485 I2CMIF_BIT);
486 } else { /* wait-event timeout */
487 pch_i2c_stop(adap);
488 return -ETIME;
489 }
490 }
491
492 /* check if this is the last message */
493 if (last)
494 pch_i2c_stop(adap);
495 else
496 pch_i2c_repstart(adap);
497
498 pch_dbg(adap, "return=%d\n", wrcount);
499
500 return wrcount;
501 }
502
503 /**
504 * pch_i2c_sendack() - send ACK
505 * @adap: Pointer to struct i2c_algo_pch_data.
506 */
507 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
508 {
509 void __iomem *p = adap->pch_base_address;
510 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
511 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
512 }
513
514 /**
515 * pch_i2c_sendnack() - send NACK
516 * @adap: Pointer to struct i2c_algo_pch_data.
517 */
518 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
519 {
520 void __iomem *p = adap->pch_base_address;
521 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
522 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
523 }
524
525 /**
526 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
527 * @adap: Pointer to struct i2c_algo_pch_data.
528 *
529 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
530 */
531 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
532 {
533 void __iomem *p = adap->pch_base_address;
534 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
535 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
536 }
537
538 /**
539 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
540 * @i2c_adap: Pointer to the struct i2c_adapter.
541 * @msgs: Pointer to i2c_msg structure.
542 * @last: specifies whether last message or not.
543 * @first: specifies whether first message or not.
544 */
545 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
546 u32 last, u32 first)
547 {
548 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
549
550 u8 *buf;
551 u32 count;
552 u32 length;
553 u32 addr;
554 u32 addr_2_msb;
555 u32 addr_8_lsb;
556 void __iomem *p = adap->pch_base_address;
557 s32 rtn;
558
559 length = msgs->len;
560 buf = msgs->buf;
561 addr = msgs->addr;
562
563 /* enable master reception */
564 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
565
566 if (first) {
567 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
568 return -ETIME;
569 }
570
571 if (msgs->flags & I2C_M_TEN) {
572 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
573 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
574 if (first)
575 pch_i2c_start(adap);
576
577 rtn = pch_i2c_wait_for_xfer_complete(adap);
578 if (rtn == 0) {
579 if (pch_i2c_getack(adap)) {
580 pch_dbg(adap, "Receive NACK for slave address"
581 "setting\n");
582 return -EIO;
583 }
584 addr_8_lsb = (addr & I2C_ADDR_MSK);
585 iowrite32(addr_8_lsb, p + PCH_I2CDR);
586 } else if (rtn == -EIO) { /* Arbitration Lost */
587 pch_err(adap, "Lost Arbitration\n");
588 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
589 I2CMAL_BIT);
590 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
591 I2CMIF_BIT);
592 pch_i2c_init(adap);
593 return -EAGAIN;
594 } else { /* wait-event timeout */
595 pch_i2c_stop(adap);
596 return -ETIME;
597 }
598 pch_i2c_restart(adap);
599 rtn = pch_i2c_wait_for_xfer_complete(adap);
600 if (rtn == 0) {
601 if (pch_i2c_getack(adap)) {
602 pch_dbg(adap, "Receive NACK for slave address"
603 "setting\n");
604 return -EIO;
605 }
606 addr_2_msb |= I2C_RD;
607 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
608 p + PCH_I2CDR);
609 } else if (rtn == -EIO) { /* Arbitration Lost */
610 pch_err(adap, "Lost Arbitration\n");
611 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
612 I2CMAL_BIT);
613 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
614 I2CMIF_BIT);
615 pch_i2c_init(adap);
616 return -EAGAIN;
617 } else { /* wait-event timeout */
618 pch_i2c_stop(adap);
619 return -ETIME;
620 }
621 } else {
622 /* 7 address bits + R/W bit */
623 addr = (((addr) << 1) | (I2C_RD));
624 iowrite32(addr, p + PCH_I2CDR);
625 }
626
627 /* check if it is the first message */
628 if (first)
629 pch_i2c_start(adap);
630
631 rtn = pch_i2c_wait_for_xfer_complete(adap);
632 if (rtn == 0) {
633 if (pch_i2c_getack(adap)) {
634 pch_dbg(adap, "Receive NACK for slave address"
635 "setting\n");
636 return -EIO;
637 }
638 } else if (rtn == -EIO) { /* Arbitration Lost */
639 pch_err(adap, "Lost Arbitration\n");
640 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
641 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
642 pch_i2c_init(adap);
643 return -EAGAIN;
644 } else { /* wait-event timeout */
645 pch_i2c_stop(adap);
646 return -ETIME;
647 }
648
649 if (length == 0) {
650 pch_i2c_stop(adap);
651 ioread32(p + PCH_I2CDR); /* Dummy read needs */
652
653 count = length;
654 } else {
655 int read_index;
656 int loop;
657 pch_i2c_sendack(adap);
658
659 /* Dummy read */
660 for (loop = 1, read_index = 0; loop < length; loop++) {
661 buf[read_index] = ioread32(p + PCH_I2CDR);
662
663 if (loop != 1)
664 read_index++;
665
666 rtn = pch_i2c_wait_for_xfer_complete(adap);
667 if (rtn == 0) {
668 if (pch_i2c_getack(adap)) {
669 pch_dbg(adap, "Receive NACK for slave"
670 "address setting\n");
671 return -EIO;
672 }
673 } else { /* wait-event timeout */
674 pch_i2c_stop(adap);
675 return -ETIME;
676 }
677
678 } /* end for */
679
680 pch_i2c_sendnack(adap);
681
682 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
683
684 if (length != 1)
685 read_index++;
686
687 rtn = pch_i2c_wait_for_xfer_complete(adap);
688 if (rtn == 0) {
689 if (pch_i2c_getack(adap)) {
690 pch_dbg(adap, "Receive NACK for slave"
691 "address setting\n");
692 return -EIO;
693 }
694 } else { /* wait-event timeout */
695 pch_i2c_stop(adap);
696 return -ETIME;
697 }
698
699 if (last)
700 pch_i2c_stop(adap);
701 else
702 pch_i2c_repstart(adap);
703
704 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
705 count = read_index;
706 }
707
708 return count;
709 }
710
711 /**
712 * pch_i2c_cb() - Interrupt handler Call back function
713 * @adap: Pointer to struct i2c_algo_pch_data.
714 */
715 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
716 {
717 u32 sts;
718 void __iomem *p = adap->pch_base_address;
719
720 sts = ioread32(p + PCH_I2CSR);
721 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
722 if (sts & I2CMAL_BIT)
723 adap->pch_event_flag |= I2CMAL_EVENT;
724
725 if (sts & I2CMCF_BIT)
726 adap->pch_event_flag |= I2CMCF_EVENT;
727
728 /* clear the applicable bits */
729 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
730
731 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
732
733 wake_up(&pch_event);
734 }
735
736 /**
737 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
738 * @irq: irq number.
739 * @pData: cookie passed back to the handler function.
740 */
741 static irqreturn_t pch_i2c_handler(int irq, void *pData)
742 {
743 u32 reg_val;
744 int flag;
745 int i;
746 struct adapter_info *adap_info = pData;
747 void __iomem *p;
748 u32 mode;
749
750 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
751 p = adap_info->pch_data[i].pch_base_address;
752 mode = ioread32(p + PCH_I2CMOD);
753 mode &= BUFFER_MODE | EEPROM_SR_MODE;
754 if (mode != NORMAL_MODE) {
755 pch_err(adap_info->pch_data,
756 "I2C-%d mode(%d) is not supported\n", mode, i);
757 continue;
758 }
759 reg_val = ioread32(p + PCH_I2CSR);
760 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
761 pch_i2c_cb(&adap_info->pch_data[i]);
762 flag = 1;
763 }
764 }
765
766 return flag ? IRQ_HANDLED : IRQ_NONE;
767 }
768
769 /**
770 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
771 * @i2c_adap: Pointer to the struct i2c_adapter.
772 * @msgs: Pointer to i2c_msg structure.
773 * @num: number of messages.
774 */
775 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
776 struct i2c_msg *msgs, s32 num)
777 {
778 struct i2c_msg *pmsg;
779 u32 i = 0;
780 u32 status;
781 u32 msglen;
782 u32 subaddrlen;
783 s32 ret;
784
785 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
786
787 ret = mutex_lock_interruptible(&pch_mutex);
788 if (ret)
789 return -ERESTARTSYS;
790
791 if (adap->p_adapter_info->pch_i2c_suspended) {
792 mutex_unlock(&pch_mutex);
793 return -EBUSY;
794 }
795
796 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
797 adap->p_adapter_info->pch_i2c_suspended);
798 /* transfer not completed */
799 adap->pch_i2c_xfer_in_progress = true;
800
801 for (i = 0; i < num && ret >= 0; i++) {
802 pmsg = &msgs[i];
803 pmsg->flags |= adap->pch_buff_mode_en;
804 status = pmsg->flags;
805 pch_dbg(adap,
806 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
807 /* calculate sub address length and message length */
808 /* these are applicable only for buffer mode */
809 subaddrlen = pmsg->buf[0];
810 /* calculate actual message length excluding
811 * the sub address fields */
812 msglen = (pmsg->len) - (subaddrlen + 1);
813
814 if ((status & (I2C_M_RD)) != false) {
815 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
816 (i == 0));
817 } else {
818 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
819 (i == 0));
820 }
821 }
822
823 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
824
825 mutex_unlock(&pch_mutex);
826
827 return (ret < 0) ? ret : num;
828 }
829
830 /**
831 * pch_i2c_func() - return the functionality of the I2C driver
832 * @adap: Pointer to struct i2c_algo_pch_data.
833 */
834 static u32 pch_i2c_func(struct i2c_adapter *adap)
835 {
836 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
837 }
838
839 static struct i2c_algorithm pch_algorithm = {
840 .master_xfer = pch_i2c_xfer,
841 .functionality = pch_i2c_func
842 };
843
844 /**
845 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
846 * @adap: Pointer to struct i2c_algo_pch_data.
847 */
848 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
849 {
850 void __iomem *p = adap->pch_base_address;
851
852 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
853
854 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
855
856 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
857 }
858
859 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
860 const struct pci_device_id *id)
861 {
862 void __iomem *base_addr;
863 int ret;
864 int i, j;
865 struct adapter_info *adap_info;
866 struct i2c_adapter *pch_adap;
867
868 pch_pci_dbg(pdev, "Entered.\n");
869
870 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
871 if (adap_info == NULL) {
872 pch_pci_err(pdev, "Memory allocation FAILED\n");
873 return -ENOMEM;
874 }
875
876 ret = pci_enable_device(pdev);
877 if (ret) {
878 pch_pci_err(pdev, "pci_enable_device FAILED\n");
879 goto err_pci_enable;
880 }
881
882 ret = pci_request_regions(pdev, KBUILD_MODNAME);
883 if (ret) {
884 pch_pci_err(pdev, "pci_request_regions FAILED\n");
885 goto err_pci_req;
886 }
887
888 base_addr = pci_iomap(pdev, 1, 0);
889
890 if (base_addr == NULL) {
891 pch_pci_err(pdev, "pci_iomap FAILED\n");
892 ret = -ENOMEM;
893 goto err_pci_iomap;
894 }
895
896 /* Set the number of I2C channel instance */
897 adap_info->ch_num = id->driver_data;
898
899 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
900 KBUILD_MODNAME, adap_info);
901 if (ret) {
902 pch_pci_err(pdev, "request_irq FAILED\n");
903 goto err_request_irq;
904 }
905
906 for (i = 0; i < adap_info->ch_num; i++) {
907 pch_adap = &adap_info->pch_data[i].pch_adapter;
908 adap_info->pch_i2c_suspended = false;
909
910 adap_info->pch_data[i].p_adapter_info = adap_info;
911
912 pch_adap->owner = THIS_MODULE;
913 pch_adap->class = I2C_CLASS_HWMON;
914 strcpy(pch_adap->name, KBUILD_MODNAME);
915 pch_adap->algo = &pch_algorithm;
916 pch_adap->algo_data = &adap_info->pch_data[i];
917
918 /* base_addr + offset; */
919 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
920
921 pch_adap->dev.parent = &pdev->dev;
922
923 pch_i2c_init(&adap_info->pch_data[i]);
924
925 pch_adap->nr = i;
926 ret = i2c_add_numbered_adapter(pch_adap);
927 if (ret) {
928 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
929 goto err_add_adapter;
930 }
931 }
932
933 pci_set_drvdata(pdev, adap_info);
934 pch_pci_dbg(pdev, "returns %d.\n", ret);
935 return 0;
936
937 err_add_adapter:
938 for (j = 0; j < i; j++)
939 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
940 free_irq(pdev->irq, adap_info);
941 err_request_irq:
942 pci_iounmap(pdev, base_addr);
943 err_pci_iomap:
944 pci_release_regions(pdev);
945 err_pci_req:
946 pci_disable_device(pdev);
947 err_pci_enable:
948 kfree(adap_info);
949 return ret;
950 }
951
952 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
953 {
954 int i;
955 struct adapter_info *adap_info = pci_get_drvdata(pdev);
956
957 free_irq(pdev->irq, adap_info);
958
959 for (i = 0; i < adap_info->ch_num; i++) {
960 pch_i2c_disbl_int(&adap_info->pch_data[i]);
961 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
962 }
963
964 if (adap_info->pch_data[0].pch_base_address)
965 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
966
967 for (i = 0; i < adap_info->ch_num; i++)
968 adap_info->pch_data[i].pch_base_address = 0;
969
970 pci_set_drvdata(pdev, NULL);
971
972 pci_release_regions(pdev);
973
974 pci_disable_device(pdev);
975 kfree(adap_info);
976 }
977
978 #ifdef CONFIG_PM
979 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
980 {
981 int ret;
982 int i;
983 struct adapter_info *adap_info = pci_get_drvdata(pdev);
984 void __iomem *p = adap_info->pch_data[0].pch_base_address;
985
986 adap_info->pch_i2c_suspended = true;
987
988 for (i = 0; i < adap_info->ch_num; i++) {
989 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
990 /* Wait until all channel transfers are completed */
991 msleep(20);
992 }
993 }
994
995 /* Disable the i2c interrupts */
996 for (i = 0; i < adap_info->ch_num; i++)
997 pch_i2c_disbl_int(&adap_info->pch_data[i]);
998
999 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
1000 "invoked function pch_i2c_disbl_int successfully\n",
1001 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
1002 ioread32(p + PCH_I2CESRSTA));
1003
1004 ret = pci_save_state(pdev);
1005
1006 if (ret) {
1007 pch_pci_err(pdev, "pci_save_state\n");
1008 return ret;
1009 }
1010
1011 pci_enable_wake(pdev, PCI_D3hot, 0);
1012 pci_disable_device(pdev);
1013 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1014
1015 return 0;
1016 }
1017
1018 static int pch_i2c_resume(struct pci_dev *pdev)
1019 {
1020 int i;
1021 struct adapter_info *adap_info = pci_get_drvdata(pdev);
1022
1023 pci_set_power_state(pdev, PCI_D0);
1024 pci_restore_state(pdev);
1025
1026 if (pci_enable_device(pdev) < 0) {
1027 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
1028 return -EIO;
1029 }
1030
1031 pci_enable_wake(pdev, PCI_D3hot, 0);
1032
1033 for (i = 0; i < adap_info->ch_num; i++)
1034 pch_i2c_init(&adap_info->pch_data[i]);
1035
1036 adap_info->pch_i2c_suspended = false;
1037
1038 return 0;
1039 }
1040 #else
1041 #define pch_i2c_suspend NULL
1042 #define pch_i2c_resume NULL
1043 #endif
1044
1045 static struct pci_driver pch_pcidriver = {
1046 .name = KBUILD_MODNAME,
1047 .id_table = pch_pcidev_id,
1048 .probe = pch_i2c_probe,
1049 .remove = __devexit_p(pch_i2c_remove),
1050 .suspend = pch_i2c_suspend,
1051 .resume = pch_i2c_resume
1052 };
1053
1054 static int __init pch_pci_init(void)
1055 {
1056 return pci_register_driver(&pch_pcidriver);
1057 }
1058 module_init(pch_pci_init);
1059
1060 static void __exit pch_pci_exit(void)
1061 {
1062 pci_unregister_driver(&pch_pcidriver);
1063 }
1064 module_exit(pch_pci_exit);
1065
1066 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
1067 MODULE_LICENSE("GPL");
1068 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.lapis-semi.com>");
1069 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
1070 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));